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參數(shù)資料
| 型號(hào)： | MC68160FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | ENHANCED ETHERNET INTERFACE TRANSCEIVER |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP52 |
| 封裝： | PLASTIC, TQFP-52 |
| 文件頁(yè)數(shù)： | 12/30頁(yè) |
| 文件大小： | 372K |
| 代理商： | MC68160FB |
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MC68160 MC68160B MC68160C
12
MOTOROLA ANALOG IC DEVICE DATA
AC ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, minimum and maximum limits apply over the recommended
temperature and power supply voltage ranges for each MC68160, B, C except where noted.)
Characteristic
Symbol
Min
Max
Unit
EXTERNAL CLOCK INPUT (X1)
Cycle Time (Note 1) (See Figure 8)
Fall Time
Rise Time
Low Time
High Time
t1
t2
t3
t4
t5
49.995
–
–
20
20
50.005
5.0
5.0
30
30
ns
RECEIVE PHASE–LOCKED–LOOP SWITCHING
Stabilization Time
t7
–
100
ms
CONTROLLER TRANSMIT SWITCHING (MOTOROLA MODE)
TCLK Cycle Time
TCLK High Time
TCLK Low Time
TCLK Rise and Fall Time
t10
t11
t12
t13
t14
t15
99
45
45
–
101
55
55
8.0
ns
TX Setup Time to TCLK
↑
TX Hold Time to TCLK
↑
20
0
–
–
ns
TENA Setup Time to TCLK
↑
TENA Hold Time to TCLK
↑
t16
t17
20
0
–
–
ns
CONTROLLER RECEIVE SWITCHING
RCLK Cycle Time
RCLK High Time
RCLK Low Time (MC68160, MC68160C)
RCLK Low Time (MC68160B)
RCLK Rise and Fall Time
t20
t21
t22
t22
t23
t24
t24.1
90
42
47
44
–
–
–
55
58
8.0
ns
RX Hold Time from RCLK
↑
RX Set–Up Time to RCLK
↑
10
70
–
–
ns
RCLK Delay from RENA
↑
RX Delay from RENA
↑
t25
t26
–
–
650
600
ns
RENA Deassertion Delay from RCLK
↑
(See Figure 12)
t27
10
30
ns
NOTES:
1. To meet IEEE–802.3 specifications.
2. Load on specified output is 20 pF to ground, unless otherwise noted.
3.
↑
= Rising Edge
t1
4.0V
3.6V
0.4V
0V
3.6V
0.4V
1.5V
1.5V
1.5V
t2
t3
t4
t5
Figure 8. X1 Input Voltage Levels for Timing Measurements
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