參數(shù)資料
型號(hào)： MC68334GMFC16
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 16 MHz, MICROCONTROLLER, PQFP132
封裝： PLASTIC, QFP-132
文件頁數(shù)： 15/76頁
文件大小： 444K
代理商： MC68334GMFC16
MOTOROLA
MC68334
22
MC68334TS/D REV. 1
3.3.4 Low-Power Operation
Low-power operation is initiated by the CPU32. To reduce power consumption selectively, the CPU can
set the STOP bits in each module configuration register. To minimize overall microcontroller power con-
sumption, the CPU can execute the LPSTOP instruction, which causes the SIM to turn off the system
clock.
When individual module STOP bits are set, clock signals inside each module are turned off, but module
registers are still accessible.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the current interrupt
mask into the clock control logic. The SIM brings the MCU out of low-power operation when either an
interrupt of higher priority than the stored mask or a reset occurs.
During a low-power stop, unless the system clock signal is supplied by an external source and that
source is removed, the SIM clock control logic and the SIM clock signal (SIMCLK) continue to operate.
The periodic interrupt timer and input logic for the RESET and IRQ pins are clocked by SIMCLK. The
SIM can also continue to generate the CLKOUT signal while in low-power mode.
The stop mode system integration module clock (STSIM) and stop mode external clock (STEXT) bits in
SYNCR determine clock operation during low-power stop. The table below summarizes the effects of
STSIM and STEXT. MODCLK value is the logic level on the MODCLK pin during the last reset before
LPSTOP execution. Any clock in the off state is held low. If the synthesizer VCO is turned off during
LPSTOP, there is a PLL relock delay after the VCO is turned back on.
3.3.5 Loss of Reference Signal
The state of the reset enable (RSTEN) bit in SYNCR determines what happens when clock logic detects
a reference failure.
When RSTEN is cleared (default state out of reset), the clock synthesizer is forced into an operating
condition referred to as limp mode. Limp mode frequency varies from device to device, but maxi-
Table 8 Clock Control
Mode
Pins
SYNCR Bits
Clock Status
LPSTOP
MODCLK
EXTAL
STSIM
STEXT
SIMCLK
CLKOUT
ECLK
No
0
External
Clock
X
External
Clock
External
Clock
External
Clock
Yes
0
External
Clock
0
External
Clock
Off
Yes
0
External
Clock
0
1
External
Clock
External
Clock
External
Clock
Yes
0
External
Clock
1
0
External
Clock
Off
Yes
0
External
Clock
1
External
Clock
External
Clock
External
Clock
No
1
Crystal or
Reference
X
VCO
Yes
1
Crystal or
Reference
0
Crystal or
Reference
Off
Yes
1
Crystal or
Reference
0
1
Crystal or
Reference
Crystal/
Reference
Off
Yes
1
Crystal or
Reference
1
0
VCO
Off
Yes
1
Crystal or
Reference
1
VCO
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