MOTOROLA
MC68336/376
I-16
USER’S MANUAL
mask register (IMASK) D-96
module configuration register (CANMCR) D-85
receive
buffer 14 mask registers (RX14MSKHI/LO)
D-93
buffer 15 mask registers (RX15MSKHI/LO)
D-93
global
mask
registers
(RXGMSKLO/HI
D-93
RX/TX error counter registers (RXECTR/TXEC-
TR) D-97
test configuration register (CANTCR) D-88
special operating modes 13-16
auto power save mode 13-18
debug mode 13-16
low-power stop mode 13-17
transmit process 13-12
TPU
A mask functions 11-6
discrete input/output (DIO) 11-6
input capture/input transition counter (ITC) 11-6
output compare (OC) 11-7
period
/pw accumulator (PPWA) 11-9
measurement
add transition detect (PMA) 11-8
missing transition detect (PMM) 11-8
position-synch pulse generator (PSP) 11-8
pulse width modulation (PWM) 11-7
quadrature decode (QDEC) 11-10
stepper motor (SM) 11-9
synch pw modulation (SPWM) 11-7
address map D-73
block diagram 11-1
components 11-2
features 3-2
FREEZE flag (TPUF) D-77
function library 11-5
G mask functions 11-10
brushless motor commutation (COMM) 11-12
fast quadrature decode (FQD) 11-12
frequency measurement (FQM) 11-13
hall effect decode (HALLD) 11-13
multichannel pulse width modulation (PCPWM)
11-11
new input capture/transition counter (NITC)
11-11
programmable time accumulator (PTA) 11-11
queued output match (QOM) 11-11
table stepper motor (TSM) 11-10
universal
asynchronous
receiver/transmitter
(UART) 11-12
host interface 11-3
interrupts 11-5
microengine 11-3
operation 11-3
coherency 11-4
emulation support 11-5
event timing 11-3
interchannel communication 11-4
programmable channel service priority 11-4
overview 11-1
parameter RAM 11-3, D-80
address map D-81
registers
channel
function select registers (CFSR) D-78
interrupt
enable register (CIER) 11-5, D-77
status register (CISR) 11-5, D-80
priority registers (CPR) D-79
decoded channel number register (DCNR) D-80
development
support control register (DSCR) D-75
support status register (DSSR) D-76
host
sequence registers (HSQR) D-78
service request registers (HSSR) D-79
link register (LR) D-80
module configuration register (TPUMCR) D-73
service grant latch register (SGLR) D-80
test configuration register (TCR) D-75
TPU interrupt configuration register (TICR) D-77
scheduler 11-3
time
bases 11-2
timer channels 11-2
timing (electricals) A-26
TPU Reference Manual 11-3, 11-16, 11-17
TPUF D-77
TPUMCR 11-13, D-73
TPURAM
address map D-82
array
address mapping 12-1
base address (ADDR) D-83
space (RASP) D-82
features 3-2
general 12-1
operation
normal 12-2
standby 12-2
privilege level 12-2
register block 12-1
registers
base address and status register (TRAMBAR)
D-82
module
configuration
register
(TRAMMCR)
D-82
test register (TRAMTST) D-82
reset 12-3
TPU microcode emulation 12-3
tPWMAX 10-17
tPWMIN 10-17
TR D-54
Trace
enable field (T) D-3
on instruction execution 4-18
TRAMBAR 12-1, D-82
TRAMMCR 12-1, D-82
336376UMBook Page 16 Friday, November 15, 1996 2:09 PM