MOTOROLA
MC68336/376
viii
USER’S MANUAL
(Continued)
Paragraph
Title
Page
TABLE OF CONTENTS
8.5
QADC Bus Interface .................................................................................. 8-6
8.6
Module Configuration ................................................................................ 8-6
8.6.1
Low-Power Stop Mode ...................................................................... 8-6
8.6.2
Freeze Mode ..................................................................................... 8-7
8.6.3
Supervisor/Unrestricted Address Space ........................................... 8-7
8.6.4
Interrupt Arbitration Priority ............................................................... 8-8
8.7
Test Register ............................................................................................. 8-8
8.8
General-Purpose I/O Port Operation ......................................................... 8-8
8.8.1
Port Data Register ............................................................................. 8-9
8.8.2
Port Data Direction Register .............................................................. 8-9
8.9
External Multiplexing Operation .............................................................. 8-10
8.10
Analog Input Channels ............................................................................ 8-12
8.11
Analog Subsystem .................................................................................. 8-12
8.11.1
Conversion Cycle Times ................................................................. 8-13
8.11.1.1
Amplifier Bypass Mode Conversion Timing ............................ 8-14
8.11.2
Front-End Analog Multiplexer .......................................................... 8-15
8.11.3
Digital to Analog Converter Array .................................................... 8-15
8.11.4
Comparator ..................................................................................... 8-16
8.11.5
Successive Approximation Register ................................................ 8-16
8.12
Digital Control Subsystem ....................................................................... 8-16
8.12.1
Queue Priority ................................................................................. 8-16
8.12.2
Queue Boundary Conditions ........................................................... 8-19
8.12.3
Scan Modes .................................................................................... 8-20
8.12.3.1
Disabled Mode and Reserved Mode ....................................... 8-20
8.12.3.2
Single-Scan Modes ................................................................. 8-20
8.12.3.3
Continuous-Scan Modes ......................................................... 8-22
8.12.4
QADC Clock (QCLK) Generation .................................................... 8-24
8.12.5
Periodic/Interval Timer .................................................................... 8-27
8.12.6
Control and Status Registers .......................................................... 8-28
8.12.6.1
Control Register 0 (QACR0) ................................................... 8-28
8.12.6.2
Control Register 1 (QACR1) ................................................... 8-28
8.12.6.3
Control Register 2 (QACR2) ................................................... 8-28
8.12.6.4
Status Register (QASR) .......................................................... 8-28
8.12.7
Conversion Command Word Table ................................................. 8-28
8.12.8
Result Word Table ........................................................................... 8-31
8.13
Interrupts ................................................................................................. 8-32
8.13.1
Interrupt Sources ............................................................................. 8-32
8.13.2
Interrupt Register ............................................................................. 8-32
8.13.3
Interrupt Vectors .............................................................................. 8-33
8.13.4
Initializing the QADC for Interrupt Driven Operation ....................... 8-34
SECTION 9 QUEUED SERIAL MODULE
336376UMBook Page viii Friday, November 15, 1996 2:09 PM