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| 型號： | MC68360UMAD |
| 廠商： | Motorola, Inc. |
| 英文描述： | Errata and Added Information to MC68360 Quad Integrated Communication Controller User Manual Rev 1 |
| 中文描述： | 勘誤表和新增的資料MC68360四綜合通信控制器用戶手冊修訂1 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 159K |
| 代理商： | MC68360UMAD |
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MOTOROLA
MC68360 USER’S MANUAL ERRATA
13
0 = collision is sensed after 1/2 bit delay
(or at 3/4 bit delay if the clock duty cycle is 25%).
1 = collision is sensed after one bit delay
21. Corrections for HDLC Mode Register PSMR[DRT] Bit Description.
On page 7-179, replace the DRT—Disable Receiver While Transmitting description with the
following:
DRT—Disable Receiver While Transmitting
0 = Normal operation
1 = Reserved—not allowed in HDLC bus mode. Use address filtering to implement
the same functionality.
22. Missing boldface for HDLC RxBD control bits.
On the top of page 7-181, the
boldfaced to denote user-initialized.
E
,
W
,
I
, and
CM
control bits of the HDLC RxBD should be
23. Corrections for Transparent Event Register (SCCE).
On page 7-232, section 7.10.21.11, make the following corrections:
a) ‘RCH’ in the table should be ‘—’.
b) Reserved bits (indicated below table) should include bit 3.
c) RCH—Receive Character text description should be removed.
24. Missing Note on Ethernet Collision.
On Page 7-241, section 7.10.23.5, the following note should be added at the end of the third
paragraph:
NOTE
If an Ethernet frame is made up of multiple buffers, the user
should not reuse the first buffer descriptor until the last buffer de-
scriptor of the frame has had its ready bit cleared by the CPM.
25. Typo on MAXD1 and MAXD2 Value.
On pages 7-247 and 7-249, the manual states that the user should set this parameter to
1518 decimal. The user should instead set the parameter to 1520 decimal.
26. Wrong font on DMA_cnt.
On page 7-247, Table 7-11. The parameter DMA_cnt was printed with a bold face indicating
that the parameter should be initialized by user. This is not correct DMA_cnt does not need
to be initialized by the user and should have been in plain font.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68360CFE25 | QUad Integrated Communications Controller Users Manual |
| MC68360CRC25 | QUad Integrated Communications Controller Users Manual |
| MC68360FE25 | QUad Integrated Communications Controller Users Manual |
| MC68360FE25V | QUad Integrated Communications Controller Users Manual |
| MC68360FE33 | QUad Integrated Communications Controller Users Manual |
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| MC68360VR25LR2 | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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| MC68360VR25VLR2 | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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