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| 型號： | MC68360UMAD |
| 廠商： | Motorola, Inc. |
| 英文描述： | Errata and Added Information to MC68360 Quad Integrated Communication Controller User Manual Rev 1 |
| 中文描述： | 勘誤表和新增的資料MC68360四綜合通信控制器用戶手冊修訂1 |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 159K |
| 代理商： | MC68360UMAD |
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18
MC68360 USER’S MANUAL ERRATA
MOTOROLA
2. DC ELECTRICAL SPECIFICATIONS
On Page 10-5, Figure 10-5, some specifications were incorrectly printed. The correct spec-
ifications are as follows:
3. Removal of specification on Vcc ramp.
On page 10-5,the specification tRamp has been removed. For more information see Error
in slave mode bus arbitration diagram. on page 3 of this document.
4. Typo on CLKO2 Rise and Fall Time.
On page 10-7, the specification 4A, 5A for 33MHz was printed incorrectly. The correct spec-
ification is 1.6ns max, not 2ns.
5. Error and Missing Specification.
The following table corrects errors in Table 10.9 on page 10-9.
Characteristic
Symbol
Iin
Min
-2.5
Max
2.5
Unit
μ
A
Input Leakage Current (All Input Only Pins except TMS, TDI, and TRST)
Vin = 0/5 V
Input Leakage Current (All Input Only Pins except TMS, TDI, and TRST)
Vin = 0.5/2.4 V
Hi-Z (Off-state) Leakage Current (All Non-crystal Outputs and I/O Pins ex-
cept TMS, TDI, and TRST). Vin = 0/5 V
Hi-Z (Off-state) Leakage Current (All Non-crystal Outputs and I/O Pins)
except TMS, TDI, and TRST. Vin = 0.5/2.4 V
Output Low Voltage (For 3.3 volt part)
I
OL = 2.0 mAA31–A0, FC3–0, SIZ0–1, D31–D0,
CLKO1–2,FREEZE, IPIPE0–1,
IFETCH, BKPTO
IOL = 3.2 mA PA0, 2, 4, 6, 8–15, PB0–5, PB8–17, PC0–11,
TDO, PERR, PRTY0–3, IOUT0–2, AVECO, AS,
CAS3–0, BLCRO, RAS0–7
IOL = 5.3 mA, DSACK0–1, R/W, DS, OE, RMC,
BG, BGACK, BERR
IOL = 7 mATXD1–4
IOL =8.9 mAPB6, PB7, HALT, RESET, BR (Output)
Iin
-2.5
2.5
μ
A
IOZ
-2.5
2.5
μ
A
IOZ
-2.5
2.5
μ
A
VOL
—
0.5
0.5
0.5
0.5
0.5
V
Num.
Characteristic
Symbol
3.3 V/5.0 V
25.0 MHz
Min
-2
30
5.0V
Unit
33.34MHz
Min
-2
22.5
Max
—
—
Max
—
—
8
11A11
13A13
1410,12
14C11,13
14A
14B
CLKO1 High to Address, FC, SIZ, RMC invalid
Address, FC, SIZ, RMC Valid to CSx/RASx Asserted
tCHAZn
tAVCA
tCNAI
tSWA
tCWA
tSWAW
tSWDW
ns
ns
CSx Negated to Address, FC, SIZ Invalid (Address Hold)
30
—
22.5
—
ns
AS, CSx, OE, WE (and DS Read) Width Asserted
75
—
56.25
—
ns
CSx Width Asserted
35
—
26.25
—
ns
DS
Width Asserted (Write)
AS, CSx, OE, WE, IACKx (and DS Read) Width Asserted
(Fast Termination Cycle)
153,10,12 AS, DS, CSx, OE, WE Width Negated
17A13
18
CLKO1 High to R/W High
35
35
—
—
26.25
26.25
—
—
ns
ns
tSN
tCNRN
tCHRH
35
—
26.25
—
ns
CSx Negated to R/W High
30
—
22.5
—
ns
3
20
3
15
ns
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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