參數(shù)資料
型號(hào)： MC68C912B32FU8
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-Bit Microcontroller
中文描述： 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁(yè)數(shù)： 109/128頁(yè)
文件大?。?/td> 748K
代理商： MC68C912B32FU8
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
109
The ATD control register 2 and 3 are used to select the power up mode, interrupt control, and freeze
control. Writes to these registers abort any current conversion sequence.
Read or write anytime except ASCIF bit, which cannot be written.
Bit positions ATDCTL2[4:2] and ATDCTL3[7:2] are unused and always read as zeros.
ADPU — ATD Disable
0 = Disables the ATD, including the analog section for reduction in power consumption.
1 = Allows the ATD to function normally.
Software can disable the clock signal to the ATD converter and power down the analog circuits to re-
duce power consumption. When reset to zero, the ADPU bit aborts any conversion sequence in
progress. Because the bias currents to the analog circuits are turned off, the ATD requires a period of
recovery time to stabilize the analog circuits after setting the ADPU bit.
AFFC — ATD Fast Flag Clear All
0 = ATD flag clearing operates normally (read the status register before reading the result register
to clear the associate CCF bit).
1 = Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result
register (ATD0–7) will cause the associated CCF flag to clear automatically if it was set at the
time.
ASWAI — ATD Stop in Wait Mode
0 = ATD continues to run when the MCU is in wait mode
1 = ATD stops to save power when the MCU is in wait mode
ASCIE — ATD Sequence Complete Interrupt Enable
0 = Disables ATD interrupt
1 = Enables ATD interrupt on sequence complete
ASCIF — ATD Sequence Complete Interrupt
Cannot be written in any mode.
0 = No ATD interrupt occurred
1 = ATD sequence complete
FRZ1, FRZ0 — Background Debug (Freeze) Enable (suspend module operation at breakpoint)
When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint
is encountered. These two bits determine how the ATD will respond when background debug mode be-
comes active.
ATDCTL1 —
Reserved
$0061
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
ATDCTL2
— ATD Control Register 2
$0062
Bit 7
6
5
4
3
2
1
Bit 0
ADPU
AFFC
ASWAI
0
0
0
ASCIE
ASCIF
RESET:
0
0
0
0
0
0
0
0
ATDCTL3
— ATD Control Register 3
$0063
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
FRZ1
FRZ0
RESET:
0
0
0
0
0
0
0
0
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