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參數(shù)資料
| 型號： | MC68EC030FE40C |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT ENHANCED 132-CQFP |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 40MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-BCQFP |
| 供應(yīng)商設(shè)備封裝： | 132-CQFP（24x24） |
| 包裝： | 托盤 |
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MC68EC030 TECHNICAL DATA
MOTOROLA
The MC68EC030 instruction cache is a 256-byte direct-mapped cache organized as 16 lines consisting
of four long words per line. Each long word is independently accessible, yielding 64 possible entries, with
address bit A1 selecting the correct word during an access. Thus, each line has a tag field composed of
the upper 24 address bits, the FC2 (supervisor/user) value, four valid bits (one for each long-word entry),
and the four long-word entries (see Figure 6). The instruction cache is automatically filled by the
MC68EC030 whenever a cache miss occurs; using the burst transfer capability, up to four long words can
be filled in one burst operation. The caches cannot be manipulated directly by the programmer except by
the use of the CACR, which provides cache clearing and cache entry clearing facilities. The caches can
also be enabled/disabled by this register. Finally, the system hardware can disable the on-chip caches at
any time by asserting the
CDIS signal.
F F F
CC C 3
2 2 2 2 1 1 111111110000000000
21 0 1
3 20
1
98 7 65432109876543210
COMPARATOR
TAG
1 OF 16
SELECT
VALID
TAG REPLACE
INDEX
TAG
LINE HIT
DATA FROM INSTRUCTION
CACHE DATA BUS
CACHE CONTROL LOGIC
V
ACCESS ADDRESS
DATA TO INSTRUCTION
CACHE HOLDING REGISTER
ENTRY HIT
A
LONG WORD
SELECT
CACHE SIZE = 64 (LONG WORDS)
LINE SIZE = 4 (LONG WORDS)
SET SIZE = 1
AA AAAAAAAAAAAAAAAAAAAAAA
Figure 6.
On-Chip Instruction Cache Organization
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68EC030FE40C | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
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