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| 型號： | MC68EC030FE40C |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT ENHANCED 132-CQFP |
| 標(biāo)準包裝： | 36 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 40MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 132-BCQFP |
| 供應(yīng)商設(shè)備封裝： | 132-CQFP（24x24） |
| 包裝： | 托盤 |
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MOTOROLA
MC68EC030 TECHNICAL DATA
1 7
ACCESS CONTROL
Two access control registers are provided on the MC68EC030 to control cachability of accesses for two
independent blocks of memory. Each block can range in size from 16 Mbytes to 2 Gbytes, and is
specified in the corresponding ACx register with a base address, a base mask, function code, function
code mask, and read/write mask. A typical use for an access control register is to designate a block of
memory containing I/O devices as non-cachable.
COPROCESSOR INTERFACE
The coprocessor interface is a mechanism for extending the instruction set of the M68000 Family. The
interface provided on the MC68EC030 is the same as that on the MC68020 and MC68030. Examples of
these extensions are the addition of specialized data operands for the existing data types or, for the case
of
floating
point,
the
inclusion
of
new
data
types
and
operations
implemented
by
the
MC68881/MC68882 floating-point coprocessors.
SIGNAL DESCRIPTION
Figure 8 illustrates the functional signal groups, and Table 3 describe the signals and their function.
DSACK0
FUNCTION
CODES
ADDRESS
BUS
TRANSFER
SIZE
ASYNCHRONOUS
BUS CONTROL
CACHE
CONTROL
EMULATOR
SUPPORT
SYNCHRONOUS
BUS CONTROL
BUS EXCEPTION
CONTROL
BUS ARBITRATION
CONTROL
INTERRUPT
CONTROL
MC68EC030
FC0–FC2
A0–A31
D0–D31
SIZ0
SIZ1
OCS
ECS
R/W
RMC
AS
DS
DBEN
DSACK1
CIIN
CIOUT
CBREQ
CBACK
GND (14)
CLK
CDIS
STATUS
REFILL
STERM
BERR
HALT
RESET
IPL0
IPL1
IPL2
IPEND
AVEC
BR
BG
BGACK
V
(10)
CC
DATA
BUS
Figure 8. Functional Signal Groups
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68EC030FE40C | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
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