MO
T
O
R
OLA
10-10
MC68HC05B6
Re
v.4
CPU
CORE
AND
INSTR
UCTION
SET
10
T
a
b
le
10-9
M68HC05
opcode
map
Bit manipulation
Branch
Read/modify/write
Control
Register/memor y
BTB
BSC
REL
DIR
INH
IX1
IX
INH
IMM
DIR
EXT
IX2
IX1
IX
High
0123456789
A
B
C
D
E
F
High
Low
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Low
0
0000
553533659
234543
0
0000
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
RTI
SUB
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
1
0001
553
6
234543
1
0001
BRCLR0
BCLR0
BRN
RTS
CMP
3
BTB 2
BSC 2
REL
1
INH
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
2
0010
553
11
234543
2
0010
BRSET1
BSET1
BHI
MUL
SBC
3
BTB 2
BSC 2
REL
1
INH
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
3
0011
55353365
10
234543
3
0011
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
SWI
CPX
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
4
0100
55353365
234543
4
0100
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
AND
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
0101
553
234543
5
0101
BRCLR2
BCLR2
BCS
BIT
3
BTB 2
BSC 2
REL
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
6
0110
55353365
234543
6
0110
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
LDA
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
7
0111
55353365
2
45654
7
0111
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH
2
DIR 3
EXT 3
IX2 2
IX1 1
IX
8
1000
55353365
2234543
8
1000
BRSET4
BSET4
BHCC
LSL
LSLA
LSLX
LSL
CLC
EOR
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
9
1001
55353365
2234543
9
1001
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
SEC
ADC
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
A
1010
55353365
2234543
A
1010
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
CLI
ORA
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
B
1011
553
2234543
B
1011
BRCLR5
BCLR5
BMI
SEI
ADD
3
BTB 2
BSC 2
REL
1
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
C
1100
55353365
2
23432
C
1100
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
RSP
JMP
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH
2
DIR 3
EXT 3
IX2 2
IX1 1
IX
D
1101
55343354
2656765
D
1101
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
TST
NOP
BSR
JSR
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH 2
REL 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
E
1110
553
2
234543
E
1110
BRSET7
BSET7
BIL
STOP
LDX
3
BTB 2
BSC 2
REL
1
INH
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
F
1111
5535336522
45654
F
1111
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
CLR
WAIT
TXA
STX
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH 1
INH
2
DIR 3
EXT 3
IX2 2
IX1 1
IX
F
1111
3
0
0000
SUB
1IX
Opcode in hexadecimal
Opcode in binary
Address mode
Cycles
Bytes
Mnemonic
Legend
Abbre viations for address modes and register s
BSC
BTB
DIR
EXT
INH
IMM
IX
IX1
IX2
REL
A
X
Bit set/clear
Bit test and branch
Direct
Extended
Inherent
Immediate
Indexed (no offset)
Indexed, 1 byte (8-bit) offset
Indexed, 2 byte (16-bit) offset
Relative
Accum ulator
Index register
Not implemented
TPG
124
05B6Book
Page
10
Tuesday,
April
6,
1999
8:24
am