參數(shù)資料
型號: MC68HC05C12ACFN
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 32/156頁
文件大?。?/td> 3848K
代理商: MC68HC05C12ACFN
Electrical Specifications
3.3 V Serial Peripheral Interface Timing
MC68HC05C12A Rev. 3.0
General Release Specification
Electrical Specifications
NON-DISCLOSURE
AGREEMENT
REQUIRED
13.12 3.3 V Serial Peripheral Interface Timing
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fOP(M)
fOP(S)
dc
0.5
1.0
f
OP
MHz
1
Cycle Time
Master
Slave
tcyc(M)
tcyc(S)
2.0
1.0
t
CYC
s
2
Enable Lead Time
Master
Slave
tLead(M)
tLead(S)
500
ns
3
Enable Lag Time
Master
Slave
tLag(M)
tLag(S)
1.5
ns
s
4
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
720
400
ns
5
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
720
400
ns
6
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
200
ns
7
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
200
ns
8
Slave Access Time
(Time to Data Active from High-Impedance State)
tA
0
250
ns
9
Slave Disable Time
(Hold Time to High-Impedance State)
tDIS
500
ns
10
Data Valid
Master (Before Capture Edge)
Slave (After Enable Edge)
tV(M)
tV(S)
0.25
500
tcyc(M)
ns
11
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
tcyc(M)
ns
12
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
200
2.0
ns
s
13
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
200
2.0
ns
s
*VDD = 3.3 Vdc ± 0.3 Vdc; VSS = 0 Vdc, TA = TL to TH. Refer to Figure 13-9 and Figure 13-10 for timing diagrams.
Signal production depends on software.
Assumes 200 pF load on all SPI pins
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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