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參數(shù)資料
| 型號(hào)： | MC68HC05C12ACFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 88/156頁 |
| 文件大?。?/td> | 3848K |
| 代理商： | MC68HC05C12ACFN |
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Interrupts
Hardware Controlled Interrupt Sequence
MC68HC05C12A — Rev. 3.0
General Release Specification
Interrupts
NON-DISCLOSURE
AGREEMENT
REQUIRED
4.3 Hardware Controlled Interrupt Sequence
Three functions (RESET, STOP, and WAIT) are not in the strictest sense
interrupts; however, they are acted upon in a similar manner. Flowcharts
for hardware interrupts are shown in Figure 4-1.
1. RESET — A low input on the RESET input pin causes the program
to vector to its starting address, which is specified by the contents
of memory locations $3FFE and $3FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a
known state during this type of reset, as previously described in
2. STOP — The STOP instruction causes the oscillator to be turned
off and the processor to “sleep” until an external interrupt
(IRQ) or
reset occurs.
3. WAIT — The WAIT instruction causes all processor clocks to stop,
but leaves the timer clock running. This “rest” state of the
processor can be cleared by reset, an external interrupt (IRQ),
serial periferal interface, serial communications interface, or timer
interrupt. These individual interrupts have no special wait vectors.
4.4 Software Interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-
maskable interrupt. It is executed regardless of the state of the I bit in the
CCR. If the I bit is 0 (interrupts enabled), SWI executes after interrupts
which were pending when the SWI was fetched but before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $3FFC and
$3FFD.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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