參數(shù)資料
型號(hào): MC68HC05C8APE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 15/116頁
文件大?。?/td> 781K
代理商: MC68HC05C8APE
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
111
B.6 4.5-V to 5.5-V High-Speed SPI Timing
The data in 13.10 5.0-V Serial Peripheral Interface Timing applies to the MC68HSC05C8A with the
exceptions given here.
Num
Characteristic
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
0.5
4.1
fOP
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
244
tCYC
ns
2
Enable lead time
Master
Slave
tLead(M)
t
L
ead(S)
(1)
122
1. Signal production depends on software.
ns
3
Enable lag time
Master
Slave
tLag(M)
tLag(S)
(1)
366
ns
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
166
93
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
166
93
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
49
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
49
ns
8
Slave access time (time to data active from high-impedance state)
tA
061
ns
9
Slave disable time (hold time to high-impedance state)
tDIS
—122
ns
10
Data valid
Master (before capture edge)
Slave (after enable edge)(2)
2. Assumes 200 pF load on all SPI pins.
tV(M)
tV(S)
0.25
122
tCYC(M)
ns
11
Data hold time (outputs)
Master (after capture edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
tCYC(M)
ns
12
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
50
1.0
ns
s
13
Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
50
1.0
ns
s
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