參數(shù)資料
型號(hào): MC68HC05C8AVFB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 111/116頁
文件大小: 781K
代理商: MC68HC05C8AVFB
Electrical Specifications
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
94
Freescale Semiconductor
13.10 5.0-V Serial Peripheral Interface Timing
Num
Characteristic(1)
1. VDD = 5.0 Vdc ± 10%; VSS = 0 Vdc, TA = TL to TH. Refer to Figure 13-9 and Figure 13-10 for timing diagrams.
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
dc
0.5
2.1
fOP
MHz
1
Cycle time
Master
Slave
tCYC(M)
tCYC(S)
2.0
480
tCYC
ns
2
Enable lead time
Master
Slave
tLead(M)
tLead(S)
(2)
240
2. Signal production depends on software.
ns
3
Enable lag time
Master
Slave
t
L
ag(M)
t
L
ag(S)
(2)
720
ns
4
Clock (SCK) high time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
ns
5
Clock (SCK) low time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
ns
6
Data setup time (inputs)
Master
Slave
tSU(M)
tSU(S)
100
ns
7
Data hold time (inputs)
Master
Slave
tH(M)
tH(S)
100
ns
8
Slave access time (time-to-data active from high-impedance
state)
tA
0
120
ns
9
Slave disable time (hold time to high-impedance state)
tDIS
240
ns
10
Data valid
Master (before capture edge)
Slave (after enable edge)(3)
3. Assumes 200 pF load on all SPI pins
tV(M)
tV(S)
0.25
240
tCYC(M)
ns
11
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
tHO(M)
tHO(S)
0.25
0
tCYC(M)
ns
12
Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
100
2.0
ns
s
13
Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
100
2.0
ns
s
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