參數(shù)資料
型號(hào)： MC68HC05C8AVP
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 161/166頁
文件大小： 1914K
代理商： MC68HC05C8AVP
Serial Peripheral Interface (SPI)
Technical Data
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A — Rev. 5.0
94
Serial Peripheral Interface (SPI)
MOTOROLA
As soon as SS goes low, the transaction begins and the first edge on
SCK invokes the first data sample. When CPHA = 1, the SS pin may
be thought of as a simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Select Bits
These two bits select one of four baud rates to be used as SCK if the
device is a master; however, they have no effect in the slave mode.
10.6.2 Serial Peripheral Status Register
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
SPIF set) followed by an access of the SPDR. Unless SPSR is read
(with SPIF set) first, attempts to write to SPDR are inhibited.
Table 10-1. Serial Peripheral Rate Selection
SPR1
SPR0
Bus Clock Divided By
00
2
01
4
10
16
11
32
Address: $000B
Bit 7
654321
Bit 0
Read:
SPIF
WCOL
0
MODF
0000
Write:
Reset
000000
U
= Unimplemented
U = Unaffected
Figure 10-5. SPI Status Register (SPSR)
相關(guān)PDF資料
PDF描述
MC68HC05C8AFA 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP48
MC68HC05C8AP 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
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