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參數資料
| 型號： | MC68HC05C9AMFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 55/124頁 |
| 文件大?。?/td> | 774K |
| 代理商： | MC68HC05C9AMFN |
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Resets
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
36
Freescale Semiconductor
COPF — Computer Operating Properly Flag
Reading the COP control register clears COPF.
1 = COP or clock monitor reset has occurred.
0 = No COP or clock monitor reset has occurred.
CME — Clock Monitor Enable Bit
This bit is readable any time, but may be written only once.
1 = Clock monitor enabled
0 = Clock monitor disabled
COPE — COP Enable Bit
This bit is readable any time. COPE, CM1, and CM0 together may be written with a single write, only
once, after reset. This bit is cleared by reset.
1 = COP enabled
0 = COP disabled
CM1 — COP Mode Bit 1
Used in conjunction with CM0 to establish the COP timeout period, this bit is readable any time. COPE,
CM1, and CM0 together may be written with a single write, only once, after reset. This bit is cleared by
reset. See Table 5-1 for timeout period options.
CM0 — COP Mode Bit 0
Used in conjunction with CM1 to establish the COP timeout period, this bit is readable any time. COPE,
CM1, and CM0 together may be written with a single write, only once, after reset. This bit is cleared by
reset. See Table 5-1 for timeout period options.
Bits 7–5 — Not Used
These bits always read as 0.
Address: $001E
Bit 7
654321
Bit 0
Read:
0
COPF
CME
COPE
CM1
CM0
Write:
Reset:
000
U
0000
= Unimplemented
U = Undetermined
Figure 5-5. COP Control Register (COPCR)
Table 5-1. COP Timeout Period
CM1
CM0
fOP/2
15 Divide By
Timeout Period
(fOSC = 2.0 MHz)
Timeout Period
(fOSC = 4.0 MHz)
0
1
32.77 ms
16.38 ms
0
1
4
131.07 ms
65.54 ms
1
0
16
524.29 ms
262.14 ms
1
64
2.097 s
1.048 s
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相關代理商/技術參數 |
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