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| 型號： | MC68HC05C9AMP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 80/124頁 |
| 文件大?。?/td> | 774K |
| 代理商： | MC68HC05C9AMP |
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Transmit Data Out (TDO)
MC68HC05C9A Advance Information Data Sheet, Rev. 5.1
Freescale Semiconductor
59
9.10 Transmit Data Out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the output
line. Data format is as discussed in 9.6 Data Format and shown in Figure 9-3. The transmitter generates
a bit time by using a derivative of the RT clock, thus producing a transmission rate equal to 1/16th that of
the receiver sample clock.
9.11 SCI I/O Registers
These I/O registers control and monitor SCI operation:
SCI data register (SCDR)
SCI control register 1 (SCCR1)
SCI control register 2 (SCCR2)
SCI status register (SCSR)
9.11.1 SCI Data Register
The SCI data register (SCDR), shown in Figure 9-8, is the buffer for characters received and for
characters transmitted.
9.11.2 SCI Control Register 1
The SCI control register 1 (SCCR1), shown in Figure 9-9, has these functions:
Stores ninth SCI data bit received and ninth SCI data bit transmitted
Controls SCI character length
Controls SCI wakeup method
R8 — Bit 8 (Received)
When the SCI is receiving 9-bit characters, R8 is the ninth bit of the received character. R8 receives
the ninth bit at the same time that the SCDR receives the other eight bits. Resets have no effect on the
R8 bit.
Address: $0011
Bit 7
6543
2
1
Bit 0
Read:
SCD7
SDC6
SCD5
SCD4
SCD3
SCD2
SCD1
SCD0
Write:
Reset:
Unaffected by reset
Figure 9-8. SCI Data Register (SCDR)
Address: $000E
Bit 7
6543
2
1
Bit 0
Read:
R8
T8
M
WAKE
Write:
Reset:
U
0
U
0
= Unimplemented
U = Undetermined
Figure 9-9. SCI Control Register 1 (SCCR1)
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05C9AP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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