參數資料
型號: MC68HC05E1MDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數: 32/86頁
文件大?。?/td> 491K
代理商: MC68HC05E1MDW
General Release Specication
MC68HC05E1 — Revision 2.0
38
CPU Core
MOTOROLA
CPU Core
uses direct or extended addressing. The assembler automatically
selects the shortest form of the instruction.
3.5.4 Re;atove
The relative addressing mode is only used in branch instructions. In
relative addressing, the contents of the 8-bit signed offset byte (which is
the last byte of the instruction) is added to the PC if, and only if, the
branch conditions are true. Otherwise, control proceeds to the next
instruction. The span of relative addressing is from -128 to +127 from the
address of the next opcode. The programmer need not calculate the
offset when using the Motorola assembler, since it calculates the proper
offset and checks to see that it is within the span of the branch.
3.5.5 Indexed, No Offset
In the indexed, no offset addressing mode, the effective address of the
argument is contained in the 8-bit index register. This addressing mode
can access the first 256 memory locations. These instructions are only
one byte long. This mode is often used to move a pointer through a table
or to hold the address of a frequently referenced RAM or I/O location.
3.5.6 Indexed, 8-Bit Offset
In the indexed, 8-bit offset addressing mode, the effective address is the
sum of the contents of the unsigned 8-bit index register and the unsigned
byte following the opcode. The addressing mode is useful for selecting
the Kth element in an n element table. With this two-byte instruction, K
would typically be in X with the address of the beginning of the table in
the instruction. As such, tables may begin anywhere within the first 256
addressable locations and could extend as far as location 510. $1FE is
the last location which can be accessed in this way.
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