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參數(shù)資料
| 型號： | MC68HC05E1MDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 54/86頁 |
| 文件大?。?/td> | 491K |
| 代理商： | MC68HC05E1MDW |
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General Release Specication
MC68HC05E1 — Revision 2.0
58
Timer, Phase-Locked Loop, and Custom Periodic Interrupt
MOTOROLA
Timer, Phase-Locked Loop, and Custom Periodic
6.3 Timer
The Timer for this device is a 15-stage multi-functional ripple counter.
The features include Timer Over Flow, Power-On Reset (POR), Real
Time Interrupt, and COP Watchdog Timer.
As seen in Figure 6-1, the Timer is driven by the output of the clock
select circuit (as determined by the value of BCS in the PLLCR) then a
fixed divide by four prescaler. This signal drives an 8-bit ripple counter.
The value of this 8-bit ripple counter can be read by the CPU at any time
by accessing the Timer Counter Register (TCR) at address $09. A timer
overflow function is implemented on the last stage of this counter, giving
a possible interrupt at the rate of fop/1024. Two additional stages
produce the POR function at fop/4064. The Timer Counter Bypass
circuitry (available only in Test Mode) is at this point in the timer chain.
This circuit is followed by two more stages, with the resulting clock
(fop/16384) driving the Real Time Interrupt circuit. The RTI circuit
consists of three divider stages with a 1 of 4 selector. The output of the
RTI circuit is further divided by eight to drive the mask optional COP
Watchdog Timer circuit. The RTI rate selector bits, and the RTI and TOF
enable bits and flags are located in the Timer Control and Status
Register at location $08.
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