參數(shù)資料
型號(hào)： MC68HC05E1MDW
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁(yè)數(shù)： 19/86頁(yè)
文件大小： 709K
代理商： MC68HC05E1MDW
General Release Specication
MC68HC05E1 — Revision 2.0
26
Operating Modes
MOTOROLA
Operating Modes
2.4.3.1 Self-Check PLL Disabled
If PB2=1 and PB3=0, the self-check routine is run without turning on the
PLL. This allows the self-check program to run at any frequency, as
determined by the value of the crystal oscillator in the self-check circuit.
2.4.3.2 Jump to RAM
This routine is executed if PB2=0, PB1=1, and PB0=0.
This routine jumps to the starting address of the RAM. This is used after
a program has been placed in the RAM. This feature is useful for
production testing where single-chip timing or port functionality is
needed.
2.4.3.3 Load RAM
This routine is entered if PB2=0, PB1=1, and PB0=1.
The ldram routine does a parallel download of a program into port A
using IRQ (data ready) and PC0 (data acknowledge) to synchronize the
download with the host system. When IRQ (data ready) goes low, PC0
(data acknowledge) is deasserted and a byte of data is loaded from port
A to RAM starting at location $100. After the byte is stored in RAM, PC0
is asserted as an active low data acknowledge signal to the host. The
first byte downloaded must contain the total number of bytes to be
downloaded (program length +1). When the download is complete, the
program in RAM is executed.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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