參數(shù)資料
型號(hào)： MC68HC05E1MDW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁(yè)數(shù)： 68/86頁(yè)
文件大小： 709K
代理商： MC68HC05E1MDW
General Release Specication
MC68HC05E1 — Revision 2.0
70
Timer, Phase-Locked Loop, and Custom Periodic Interrupt
MOTOROLA
Timer, Phase-Locked Loop, and Custom Periodic
6.5.1 Custom Periodic Interrupt Control and Status Register (CPICSR) $12
The CPICSR contains the CPI flag and enable bits. Figure 6-6 shows
the location of these bits and their values after reset.
Figure 6-6. Custom Periodic Interrupt Control
and Status Register (CPICSR)
CPIF — Custom Periodic Interrupt Flag
CPIF is a clearable, read-only status bit and is set when the 15-bit
counter changes from $7FFF to $0000. A CPU interrupt request will
be generated if CPIE is set. Clearing the CPIF is done by writing a ’0’
to it. Writing a ’1’ to CPIF has no effect on the bit’s value. Reset clears
CPIF.
CPIE — Custom Periodic Interrupt Enable
When this bit is cleared, the counter is cleared and CPI interrupts are
disabled. When this bit is set, the counter starts from $0000 and a
CPU interrupt request is generated when the CPIF bit is set. Reset
clears this bit.
6.6 Operation During STOP Mode
The timer system is cleared and the CPI counter is halted when going
into STOP mode. When STOP is exited by an external interrupt or an
external RESET, the internal oscillator will resume, followed by a 4064
internal processor oscillator stabilization delay. The timer system
counter is then cleared and operation resumes. The CPI will continue
counting once the oscillator resumes and does not wait for the oscillator
to stabilize.
0
CPIE
0000
CPIF
$12
0
000000
0
RESET:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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