參數(shù)資料
型號(hào): MC68HC05E5DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 98/140頁
文件大小: 847K
代理商: MC68HC05E5DW
NON-DISCLOSURE
AGREEMENT
REQUIRED
Phase-Locked Loop (PLL) Synthesis
General Release Specification
MC68HC05E5 Rev. 1.0
60
Phase-Locked Loop (PLL) Synthesis
MOTOROLA
Figure 9-1. PLL Circuit
To change PLL frequencies, follow the procedure outlined here:
1. Clear BCS to enable the low-frequency bus rate.
2. Clear PLLON to disable the PLL and select high bandwidth.
3. Select the speed using PS1 and PS0.
4. Set PLLON to enable the PLL.
5. Wait a time of 90% tPLLS for the PLL frequency to stabilize and
select manual low bandwidth, wait another 10% tPLLS.
6. Set BCS to switch to the high-frequency bus rate
The user cannot switch among the high speeds with the BCS bit set.
Following the procedure above will prevent possible bursts of high
frequency operation during the re-configuration of the PLL.
Whenever the PLL is first enabled, the wide bandwidth mode should be
used. This enables the PLL frequency to ramp up quickly. When the
output frequency is near the desired frequency, the filter is switched to
the narrow bandwidth mode to make the final frequency more stable.
LOOP FILTER
VCO
PHASE
PCOMP
PLLOUT
FREQUENCY
DIVIDER
OSC1
XFC
CRYSTAL
OSCILLATOR
PS1
PS0
TO CLOCK
DETECT
GENERATION
CIRCUITRY
CLOCK
SELECT
BCS
0.1
F
0.1
F
VDDSYN
tREF
tFB
÷ 2
OSC1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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