參數(shù)資料
型號： MC68HC05E6VDWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： PLASTIC, SOIC-28
文件頁數(shù)： 84/140頁
文件大?。?/td> 1141K
代理商： MC68HC05E6VDWR2
Core Timer
MC68HC05E6 — Rev. 1.0
48
Core Timer
MOTOROLA
COP clear register
(COPCLR)
If the COP circuit times out, an internal reset is generated and the normal
reset vector is fetched. COP timeout is prevented by writing a ‘0’ to bit 0
(CCLR) of the COPCLR register (address $1FF0). When the COP is
cleared, only the final divide-by-eight stage is cleared (see Figure 10).
Core timer registers
Core timer control
and status register
(CTCSR)
CTOF — Core timer overflow
1 = This read-only flag is set whenever a core timer overflow
occurs.
0 = No core timer overflow has occurred.
This bit is set when the core timer counter register rolls over from $FF
to $00; an interrupt request will be generated if CTOFE is set. When
set, the bit may be cleared by writing a ‘1’ to the RCTOF bit.
RTIF — Real time interrupt flag
1 = This read-only flag is set when the pre-selected RTI period has
elapsed. The RTI period is selected using the RT0 and RT1
bits as shown in Table 8.
0 = The pre-selected RTI period has not elapsed.
This bit is set when the output of the chosen stage becomes active;
an interrupt request will be generated if RTIE is set. When set, the bit
may be cleared by writing a ‘1’ to the RRTIF bit.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
COPCLR
$1FF0
CCLR 0000 0000
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Core timer control/status (CTCSR
) $0008 CTOF
RTIF CTOFE RTIE RCTOF RRTIF
RT1
RT0 uu00 0011
4-ctimer
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