
MC68HC705J2
Rev. 2
TIMER
MOTOROLA
7-3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TOF — Timer Overflow Flag
This clearable, read-only bit becomes set when the first eight stages of the counter
roll over from $FF to $00. TOF generates a timer overflow interrupt request if
TOFE is also set. Clear TOF by writing a zero to it. Writing a one to TOF has no
effect.
RTIF — Real-Time Interrupt Flag
This clearable, read-only bit becomes set when the selected RTI output becomes
active. RTIF generates a real-time interrupt request if RTIE is also set. Clear RTIF
by writing a zero to it. Writing a one to RTIF has no effect.
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables timer overflow interrupts.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
RTIE — Real-Time Interrupt Enable
This read/write bit enables real-time interrupts
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
Bits 3 and 2 — Not used. Always read as zeros.
RT1, RT0 — Real-Time 1 and 0
These read/write bits select one of four real-time interrupt rates. See
Table 7-1
.
The real-time interrupt rate should be selected by reset initialization software. A
reset sets both RT1 and RT0, selecting the lowest real-time interrupt rate.
Changing the real-time interrupt rate near the end of the RTI period or during a
cycle in which the counter is switching can produce unpredictable results.
Because the selected RTI output drives the COP timer, changing the real-time
interrupt rate also changes the counting rate of the COP timer.
Table 7-1. Real-Time Interrupt Rate Selection
RT1:RT0
RTI Rate
RTI Period
(f
op
= 2 MHz)
8.2 ms
16.4 ms
32.8 ms
65.5 ms
COP Timeout Period
(-0/+1 RTI Period)
7
×
RTI Period
7
×
RTI Period
7
×
RTI Period
7
×
RTI Period
Minimum COP Timeout
Period ( f
op
= 2 MHz)
57.3 ms
114.7 ms
229.4 ms
458.8 ms
0 0
0 1
1 0
1 1
f
op
÷
2
14
f
op
÷
2
15
f
op
÷
2
16
f
op
÷
2
17