參數(shù)資料
型號(hào): MC68HC05J1AP
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 67/128頁
文件大?。?/td> 1650K
代理商: MC68HC05J1AP
Interrupts
Interrupt Sources
MC68HC05J1A — Rev. 3.0
Technical Data
Interrupts
Figure 4-1. External Interrupt Logic
External interrupt triggering sensitivity is a mask option. The IRQ pin can
be negative edge-triggered only or negative edge- and low
level-triggered.
With the mask option for an edge- and level-sensitive external interrupt
trigger, a falling edge or a low level on the IRQ pin latches an external
interrupt request. Edge- and level-sensitive triggering allows the use of
multiple wired-OR external interrupt sources. An external interrupt
request is latched as long as any source is holding the IRQ pin low.
With the mask option for an edge-sensitive only external interrupt trigger,
a falling edge on the IRQ pin latches an external interrupt request. A
subsequent external interrupt request can be latched only after the
voltage level on the IRQ pin returns to logic 1 and then falls again to
logic 0.
LEVEL-SENSITIVE TRIGGER
PA3
PA2
PA1
IRQ
PA0
IRQ
LATCH
VDD
(MASK OPTION)
RST
IRQ VECTOR FETCH
IRQ STATUS AND CONTROL REGISTER
EXTERNAL
INTERRUPT
REQUEST
IR
Q
E
IR
Q
F
IRQ
R
PORT A
EXTERNAL INTERRUPTS
ENABLED
(MASK OPTION)
INTERNAL DATA BUS
TO BIH & BIL
INSTRUCTION
PROCESSING
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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