參數(shù)資料
型號(hào)： MC68HC05J1AP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝： PLASTIC, DIP-20
文件頁數(shù)： 77/128頁
文件大?。?/td> 1650K
代理商： MC68HC05J1AP
Technical Data
MC68HC05J1A — Rev. 3.0
Resets
Resets
5.3.4 Illegal Address Reset
An opcode fetch from an address that is not in the ROM (locations
$0300–$07FF) or the RAM (locations $00C0–$00FF) generates an
illegal address reset.
5.4 Reset States
This subsection describes how resets initialize the MCU.
5.4.1 CPU
A reset has the following effects on the CPU:
Loads the stack pointer with $FF
Sets the I bit in the condition code register, inhibiting interrupts
Sets the IRQE bit in the interrupt status and control register
Loads the program counter with the user-defined reset vector from
locations $07FE and $07FF
Clears the stop latch, enabling the CPU clock
Clears the wait latch, waking the CPU from the wait mode
5.4.2 I/O Port Registers
A reset has these effects on I/O port registers:
Clears bits DDRA7–DDRA0 in data direction register A so that port
A pins are inputs
Clears bits PDIA7–PDIA0 in pulldown register A so that port A
pulldown devices are enabled
Clears bits DDRB5–DDRB0 in data direction register B so that port
B pins are inputs
Clears bits PDIB5–PDIB0 in pulldown register B so that port B
pulldown devices are enabled
Has no effect on port A or port B data registers
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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