參數(shù)資料
型號: MC68HC05J5ADWR2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝: SOIC-20
文件頁數(shù): 106/106頁
文件大?。?/td> 1069K
代理商: MC68HC05J5ADWR2
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
MOTOROLA
REV 2.1
B-7
Supply Current
RUN3
WAIT4
STOP5
LVR on
LVR off
IDD
6
2
40
10
4
80
30
mA
A
I/O Ports Hi-Z Leakage Current
PA0-7, PB0-5
(without individual pull-down/up activated)
IZ
——
±10
A
Input Pull-down Current
PA0-5, PB0, PB3-5
(with individual pull-down activated)
IIL
50
100
200
A
Input Pull-up Current
RESET
–50
–100
–200
A
Input Current
IRQ, OSC1
Iin
——
±1
A
Capacitance
Ports (as Input or Output)
RESET, IRQ, OSC1, OSC2/R
Cout
Cin
12
8
pF
Crystal/Ceramic Resonator Oscillator Mode
Internal Resistor
OSC1 to OSC2/R
ROSC
2
M
Pull-up Resistor
PA6, PA76
PB1, PB2
RPULLUP
2
10
5
30
10
60
K
K
LVR Trigger Voltage
VLVRI
2.7
3.0
V
TCAP Input Threshold Voltage
VTCAP
—VDD/2
V
1. VDD = 5.0Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +85°C, unless otherwise noted.
2. Typical values reect average measurements at midpoint of voltage range, 25
°C only.
3. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 (fOSC = 2.0 MHz), all
inputs 0.2 Vdc from rail; no DC loads, less than 50pF on all outputs, CL = 20 pF on OSC2/R.
4. Wait IDD: Only MFT and Timer1 active.
Wait IDD is affected linearly by the OSC2/R capacitance.
5. Stop IDD measured with OSC1 = VSS.
6. Input voltage level on PA6 or PA7 higher than 2.4V is guaranteed to be recognized as logical one and as logic
zero if lower than 0.8V. PA6 and PA7 pull-up resistor values are specied under the condition that pin voltage
ranges from 0V to 2.4V.
Table B-3. DC Electrical Characteristics, VDD=5 V
Characteristic1
Symbol
Min
Typ2
Max
Unit
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