參數(shù)資料
型號(hào)： MC68HC05J5ADWR2
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁(yè)數(shù)： 51/106頁(yè)
文件大?。?/td> 1069K
代理商： MC68HC05J5ADWR2
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
INPUT/OUTPUT PORTS
MOTOROLA
REV 2.1
7-5
corresponding I/O pin. The Port B data register is unaffected by reset. Unused bits
6 and 7 will always read as logic zeros, and any write to these bits will be ignored.
The Port B data register is unaffected by reset.
7.3.2 Port B Data Direction Register
Port B I/O pins may be programmed as an input by clearing the corresponding bit
in the DDRB, or programmed as an output by setting the corresponding bit in the
DDRB. The DDRB can be accessed at address $0005. Unused bits 6 and 7 will
always read as logic zeros, and any write to these bits will be ignored.The DDRB
is cleared by reset.
If congured as output pins, PB1 and PB2 have slow output falling-edge transition
feature. The slow transition feature is controlled by the SLOWE bit of DDRB.
SLOWE bit, if set and if the pin is congured as an output pin, enables the slow
falling-edge output transition feature of all four I/O lines, PA6, PA7, PB1 and PB2.
For the 16-pin package type, care should be taken in using PB1 pin, which is
bonded to two internal port B I/O lines PB1 and PB2, to constitute a 50mA current
sinking driver. Both PB1 and PB2 I/O lines are capable of sinking 25mA. If they
are written with the same logic 0 value in the same write cycle, PB1 pin will sink
50 mA. If they are written with different values in the same write cycle, PB1 pin will
sink only 25mA.
For the 20-pin package type, I/O lines PB1 and PB2 are not bonded to the same
pin. Hence, to constitute a 50mA current sinking driver, PB1 and PB2 pins have to
be tied together externally and controlled in the same way as in the16-pin pack-
age type case.
Also, if the slow transition feature of pin PB1 is enabled, a combination of I/O lines
PB1 and PB2, is also a combination of slow transition features of I/O lines PB1
and PB2. PB2 line falling-edge output transition occurs tCYC/2 after the write
cycle, with a standard I/O edge transition time. Whereas for PB1 line, the falling-
edge transition occurring immediately after the write cycle, but with an edge tran-
sition time slower than standard I/Os, similar to PA6 and PA7 pins.
The net result is, for the 16-pin package type, since both PB1 and PB2 I/O lines
are bonded to the same PB1 pin, the combination of delayed PB1 line sharp-edge
output and the non-delayed slow transition output yields the desired slow output
falling-edge transition.
For the 20-pin package, PB1 and PB2 pins should be tied externally to create a
driver with the desired slow output falling-edge transition feature. If SLOWE is set
and PB2 pin is not tied to PB1 pin, be advised that the output at PB2 changes
state tCYC/2 after the write cycle.
7.3.3 Port B Pulldown/up Register
All Port B I/O pins may have software programmable pulldown/up devices enabled
by a mask option. If the pulldown/up mask option is selected, the pulldown/up is
activated whenever the corresponding bit in the PDURB is clear. A pulldown on an
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