參數(shù)資料
型號(hào)： MC68HC05K3CSD
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO20
封裝： SSOP-20
文件頁(yè)數(shù)： 39/69頁(yè)
文件大?。?/td> 1383K
代理商： MC68HC05K3CSD
Technical Data
MC68HC05K3 — Rev. 5
44
Interrupts
MOTOROLA
Interrupts
If the mask option for edge-sensitive only IRQ is used, only the IRQ
latch output can activate an IRQF flag which creates a request to the
CPU to generate the IRQ interrupt sequence. This makes the IRQ
interrupt sensitive to these cases:
If the port A interrupts are disabled by a mask option, only a falling
edge on the IRQ pin initiates an IRQ interrupt.
If the port A interrupts are enabled by a mask option, these
conditions initiate an IRQ interrupt:
–
A falling edge on the IRQ pin with all the PA0–PA3 pins at a
low level
–
A rising edge on one PA0–PA3 pin with all other PA0–PA3 pins
at a low level and the IRQ pin at a high level
If the mask option for edge- and level-sensitive IRQ is used, the active
high state of the IRQ latch input also can activate an IRQF flag, which
creates a request to the CPU to generate the IRQ interrupt sequence.
This makes the IRQ interrupt sensitive to these cases:
If the port A interrupts are disabled by a mask option, only these
conditions initiate an IRQ interrupt:
–
A low level on the IRQ pin
–
Falling edge on the IRQ pin
If the port A interrupts are enabled by a mask option, these
conditions initiate an IRQ interrupt:
–
A low level on the IRQ pin with all the PA0–PA3 pins at a low
level
–
Falling edge on the IRQ pin with all the PA0–PA3 pins at a low
level
–
High level on any one of the PA0–PA3 pins with the IRQ pin at
a high level
–
Rising edge on any PA0–PA3 pin with all other PA0–PA3 pins
at a low level and the IRQ pin at a high level
The IRQE enable bit controls whether an active IRQF flag can generate
an IRQ interrupt sequence. This interrupt is serviced by the interrupt
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