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參數(shù)資料
| 型號(hào)： | MC68HC05K3CSD |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁(yè)數(shù)： | 57/69頁(yè) |
| 文件大?。?/td> | 1383K |
| 代理商： | MC68HC05K3CSD |
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Technical Data
MC68HC05K3 — Rev. 5
60
Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
7.2 Introduction
In single-chip mode, 10 bidirectional input/output (I/O) lines are arranged
as one 8-bit I/O port (port A) and one 2-bit I/O port (port B). The individual
bits in these ports are programmable as either inputs or outputs under
software control by the data direction registers (DDRs). All port A and
port B I/O pins have individual software programmable pulldown devices
which can be enabled by a mask option. Some port A pins also have the
additional properties of sinking higher current or acting as additional IRQ
interrupt input sources. One of the port B pins also may be used as an
output for a 3-pin resistor capacitor (RC) oscillator option.
7.3 Port A
Port A is an 8-bit bidirectional port that shares four of its pins with the IRQ
interrupt system, as shown in Figure 7-1. Each port A pin is controlled
by the corresponding bits in a data direction register, a data register, and
a pulldown register.
Figure 7-1. Port A I/O Circuitry
WRITE $0010
READ $0000
WRITE $0000
READ $0004
DATA
REGISTER BIT
TO IRQ INTERRUPT SYSTEM
(BITS 0-3 ONLY)
I/O
PIN
OUTPUT
MASK OPTION TO INHIBIT
SOFTWARE PULLDOWNS
INTERNAL HC05
DATA BUS
RESET
(RST)
WRITE $0004
DATA DIRECTION
REGISTER BIT
PULLDOWN
REGISTER BIT
VDD
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