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參數(shù)資料
| 型號： | MC68HC05P18AMP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 73/130頁 |
| 文件大小： | 1310K |
| 代理商： | MC68HC05P18AMP |
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Resets
Internal Resets
MC68HC05P18A
Technical Data
Resets
NON-DISCLOSURE
AGREEMENT
REQUIRED
5.4.1 Power-On Reset (POR)
The internal POR is generated at power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
PH2 clock cycle oscillator stabilization delay after the oscillator becomes
active.
The POR generates the RST signal and resets the MCU. At the same
time, the POR pulls the RESET pin low allowing external devices to be
reset with the MCU. If any other reset function is active at the end of this
4064 PH2 clock cycle delay, the RST signal remains active until the
other reset condition(s) end.
5.4.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled by mask option, the internal
COP reset is generated automatically by a timeout of the COP watchdog
timer. This timer is implemented with an 18-stage ripple counter that
provides a timeout period of 65.5 ms when a 4-MHz oscillator is used.
The COP watchdog counter is cleared by writing a logical 0 to bit 0 at
location $3FF0.
The COP register is shared with the most-significant bit (MSB) of an
unimplemented user interrupt vector, as shown in Figure 5-2. Reading
this location returns the MSB of the unimplemented user interrupt vector.
Writing to this location clears the COP watchdog timer.
Address:
$3FF0
Bit 7
654321
Bit 0
Read:
00000000
Write:
R
COPR
Reset:
Unaffected by reset
R
= Reserved
= Unimplemented
Figure 5-2. COP Register (COPR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05P18AP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
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