參數(shù)資料
型號: MC68HC05P9AVDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 44/90頁
文件大?。?/td> 285K
代理商: MC68HC05P9AVDW
GENERAL RELEASE SPECIFICATION
MC68HC05P9A
TIMER
MOTOROLA
Rev. 2.0
8-5
8.4
Timer Control Register (TCR) $12
The TCR is a read/write register containing ve control bits. Three bits control
interrupts associated with the timer status register ags ICF, OCF, and TOF.
ICIE — Input Capture Interrupt Enable
1 =
Interrupt enabled
0 =
Interrupt disabled
OCIE — Output Compare Interrupt Enable
1 =
Interrupt enabled
0 =
Interrupt disabled
TOIE — Timer Overow Interrupt Enable
1 =
Interrupt enabled
0 =
Interrupt disabled
IEDG — Input Edge
Value of input edge determines which level transition on TCAP pin will trigger
free-running counter transfer to the input capture register
1 =
Positive edge
0 =
Negative edge
Reset does not affect the IEDG bit (U=unaffected).
OLVL — Output Level
Value of output level is clocked into output level register by the next successful
output compare and will appear on the TCMP pin
1 =
High output
0 =
Low output
Bits 2, 3, and 4 — Not used
Always read zero
$12
ICIE
OCIE
TOIE
0
IEDG
OLVL
RESET:
00000000
Figure 8-2. Timer Control Register
相關(guān)PDF資料
PDF描述
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