參數(shù)資料
型號: MC68HC05P9AVDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 51/90頁
文件大?。?/td> 285K
代理商: MC68HC05P9AVDW
GENERAL RELEASE SPECIFICATION
MC68HC05P9A
ANALOG-TO-DIGITAL (A/D) CONVERTER
MOTOROLA
Rev. 2.0
10-1
SECTION 10
ANALOG-TO-DIGITAL (A/D) CONVERTER
This section describes the four-channel, 8-bit, multiplexed input, successive-
approximation A/D converter.
10.1
Conversion Process
The A/D conversion process is ratiometric, using two reference voltages, VRH and
VSS. Conversion accuracy is guaranteed only if VRH is equal to VDD.
A multiplexer selects one of four analog input channels (AN3, AN2, AN1, or AN0)
for sampling. A comparator successively compares the output of an internal
digital-to-analog (D/A) converter to the sampled analog input. Control logic
changes the D/A converter input one bit at a time, starting with the most
signicant bit (MSB), until the D/A converter output matches the sampled analog
input. The conversion is monotonic and has no missing codes.
An analog input voltage equal to VRH converts to digital $FF; an input voltage
greater than VRH converts to $FF with no overow. An analog input voltage equal
to VSS converts to digital $00. For ratiometric conversions, the source of each
analog input should use VRH as the supply voltage and be referenced to VSS.
Pins PC6–PC3 are the four inputs to the multiplexer. Each channel of conversion
takes 32 internal clock cycles, and the clock frequency must be equal to or greater
than 1 MHz. If the internal clock frequency is less than 1 MHz, the A/D internal RC
oscillator (nominally 1.5 MHz) must be used for the A/D conversion clock. Make
this selection by setting the ADRC bit in the A/D status and control register to
logical one.
相關(guān)PDF資料
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