參數(shù)資料
型號(hào)： MC68HC05PL4BCSD
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.56 MHz, MICROCONTROLLER, PDSO28
封裝： SSOP-28
文件頁(yè)數(shù)： 29/98頁(yè)
文件大?。?/td> 1019K
代理商： MC68HC05PL4BCSD
April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
RESETS
MOTOROLA
REV 2.0
5-3
5.3.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabi-
lize. The POR is strictly for power turn-on conditions and is not able to detect a
drop in the power supply voltage (brown-out). There is an oscillator stabilization
delay of 4064 internal processor bus clock cycles after the oscillator becomes
active.
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of the 4096 cycle delay, the RST signal will remain in
the reset condition until the other reset condition(s) end.
POR will not activate the pulldown device on the RESET pin. VDD must drop
below VPOR in order for the internal POR circuit to detect the next rise of VDD.
5.3.2 Computer Operating Properly (COP) Reset
The COP watchdog system consist of a divide by 8 counter with clock source from
the 8-bit Timer (Timer8). Hence, a COP watchdog time-out occurs on the 8th
Timer8 clock pulse. A COP watchdog time-out generates a COP reset to the CPU.
Figure 5-3 shows a block diagram of the COP watchdog logic.
Figure 5-3. COP Watchdog Block Diagram
The COP watchdog is part of a software error detection system and must be
cleared periodically to start a new time-out period. To clear the COP watchdog
and prevent a COP reset, write a logic “1” to the COPC bit in the COP register at
location $1FF0. The COP register, shown in Figure 5-4, is a write-only register
that returns the content of a ROM location when read.
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic one to COPC prevents the
COP watchdog from resetting the MCU. Reset clears the COPC bit.
1 =
Reset COP watchdog timer.
0 =
No effect on COP watchdog timer.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
COPR
R
$1FF0
W
COPC
RESET
UUUUUUUU
Figure 5-4. COP Watchdog Register (COPR)
S
Latch
R
COPON
From Timer8 Counter
÷ 8 Counter
COP Reset
To Reset Logic
Write “1” to COPC
R
Logic
From Reset Logic
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