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參數(shù)資料
| 型號： | MC68HC05PL4P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.56 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 10/98頁 |
| 文件大?。?/td> | 1019K |
| 代理商： | MC68HC05PL4P |
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GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
MEMORY
MC68HC05PL4
2-2
REV 2.0
2.2
I/O REGISTERS
The rst 32 addresses of the memory space, $0000-$001F, are the I/O section.
One I/O register is located outside the 32-byte I/O section, which is the Computer
Operating Properly (COP) register mapped at $1FF0.
The bit assignment of each I/O register is described in the respective sections and
summarized in Figure 2-3 and Figure 2-4.
2.3
RAM
The 256 addresses from $0020 to $01FF serve as both user RAM and the stack
RAM. The CPU uses ve RAM bytes to save all CPU register contents before pro-
cessing an interrupt. During a subroutine call, the CPU uses two bytes to store the
return address. The stack pointer decrements during pushes and increments dur-
ing pulls.
NOTE
Be careful when using nested subroutines or multiple interrupt levels. The CPU
may overwrite data in the RAM during a subroutine or during the interrupt stacking
operation.
2.4
ROM
The 4096 bytes of user ROM is located from address $0E00 to $1DFF.
Addresses $1FF0 to $1FFF contain 16 bytes of ROM reserved for user vectors.
2.5
COP WATCHDOG REGISTER (COPR)
Writing “0” to the COPC bit in the COP watchdog register ($1FF0) resets the COP
watchdog timer. This is a write only register; writing a “1” to COPC has no effect.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
COPR
R
$1FF0
W
COPC
RESET
UUUUUUUU
Figure 2-2. COP Watchdog Register (COPR)
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