參數(shù)資料
型號: MC68HC05PL4P
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.56 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 33/98頁
文件大?。?/td> 1019K
代理商: MC68HC05PL4P
April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
RESETS
MOTOROLA
REV 2.0
5-7
5.5
RESET CHARACTERISTICS
Table 5-1. Reset Characteristics
Figure 5-6. Stop Recovery Timing Diagram
Characteristic
Symbol
Min
Typ
Max
Unit
POR Recovery Voltage2
VPOR
0
100
mV
POR VDD Slew Rate
2
Rising2
Falling2
SVDDR
SVDDF
0.1
0.05
V/ms
RESET Pulse Width (when bus clock active)
tRL
1.5
tCYC
RESET Pulldown Pulse Width (from internal reset)
tRPD
3—4
tCYC
Note:
1.
+2.0
≤ V
DD ≤ +4.0 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2.
By design, not tested.
PCH
NEW
1FFE
t
RL
OSC1
1
RESET
Internal
Clock3
Internal
Address
Bus3
4096
NOTES:
1.
Represents the internal gating of the OSC1 pin
2.
Normal delay of 4064 tCYC
3.
Internal timing signal and data information not available externally.
Internal
Data
Bus3
1FFF
NEW PCH NEW PCL
PCL
NEW
code
Op
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