參數(shù)資料
型號(hào)： MC68HC05SR3B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP42
封裝： SDIP-42
文件頁數(shù)： 15/96頁
文件大?。?/td> 3045K
代理商： MC68HC05SR3B
Freescale
2-2
MC68HC05SR3
PIN DESCRIPTIONS
2
2.2
OSC1 and OSC2 Connections
The OSC1 and OSC2 pins are the connections for the on-chip oscillator — the following
configurations are available:
1) A crystal or ceramic resonator as shown in Figure 2-1(a).
2) An external clock signal as shown in Figure 2-1(b).
3) RC options as shown in Figure 2-1(c) and Figure 2-1(d).
PA0-PA7
33-40
34-41
42-44, 1-5
These eight I/O lines comprise port A. The state of any pin
is software programmable. All port A lines are configured as
input during power-on or external reset.
PA0-PA7 are also associated with the Keyboard Interrupt
function. Each pin is equipped with a programmable
integrated 20K pull-up resistor connected to VDD when
configured as input. When programmed as output, each pin
can provide a current drive of 10mA. See Section 3 for
details on the I/O ports.
PB0-PB7
25-32
26-33
31, 35-41
These eight I/O lines comprise port B. The state of any pin
is software programmable. All port B lines are configured as
input during power-on or external reset.
Each pin is equipped with a programmable integrated 20K
pull-up resistor connected to VDD when configured as input.
When programmed as output, each pin can provide a
current drive of 10mA. PB5-PB7 can also be programmed to
provide a lower current drive of 2mA. See Section 3 for
details on the I/O ports.
PC0-PC7
9-16
10-17
15-22
These eight I/O lines comprise port C. The state of any pin
is software programmable. All port C lines are configured as
input during power-on or external reset.
Each pin is equipped with a programmable integrated 20K
pull-up resistor connected to VDD when configured as input.
When programmed as output, each pin can provide a
current drive of 10mA. See Section 3 for details on the I/O
ports.
PD0-PD7
AN0-AN3
IRQ2
VRH
VRL
24-21, 20-17
24-21
18
19
20
25-22, 21-18
25-22
19
20
21
30-23
30-27
24
25
26
These eight I/O lines comprise port D. The state of any pin
is software programmable. All port D lines are configured as
input during power-on or external reset.
Each pin is equipped with a programmable integrated 20K
pull-up resistor connected to VDD when configured as input.
When programmed as output, each pin can provide a
current drive of 10mA.
PD0-PD3 become analog inputs AN0-AN3 when the ADON
bit is set in the ADC Status and Control Register ($0E). PD4
and PD5 becomes VRL and VRH respectively for the ADC
reference voltage inputs.
PD6 is configured as IRQ2 by setting IRQ2E in the
Miscellaneous Control Register ($0C).
See Section 3 for details on the I/O ports.
PIN NAME
40-pin PDIP
PIN No.
42-pin SDIP
PIN No.
44-pin QFP
PIN No.
DESCRIPTION
TPG
20
05SR3.Book Page 2 Thursday, August 4, 2005 1:08 PM
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