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參數資料
| 型號： | MC68HC05SR3CP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數： | 33/96頁 |
| 文件大?。?/td> | 612K |
| 代理商： | MC68HC05SR3CP |
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MC68HC05SR3
MOTOROLA
5-3
RESETS AND INTERRUPTS
5
5.2.1
Non-maskable Software Interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is
execute regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupt enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specied by
the contents of memory locations $1FFC and $1FFD.
Figure 5-1 Interrupt Stacking Order
Table 5-1 Reset/Interrupt Vector Addresses
Register
Flag Name
Interrupt
CPU Interrupt
Vector Address
Priority
—
Reset
RESET
$1FFE-$1FFF
—
Software
SWI
$1FFC-$1FFD
—
External Interrupt
IRQ
$1FFA-$1FFB
—
External Interrupt 2
IRQ2
$1FF8-$1FF9
TCR
TIF
Timer Overow
TIF
$1FF6-$1FF7
—
Keyboard
KBI
$1FF4-$1FF5
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
$00FD
$00FE
$00FF (TOP OF STACK)
UNSTACKING
1
2
3
4
5
4
3
2
1
STACKING
ORDER
highest
lowest
TPG
37
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