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參數(shù)資料
| 型號(hào)： | MC68HC05SU3AFB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 19/80頁 |
| 文件大?。?/td> | 328K |
| 代理商： | MC68HC05SU3AFB |
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MOTOROLA
3-2
MC68HC05SU3A
INPUT/OUTPUT PORTS
3
3.1.2
Port Data Direction Registers
Each port pin may be programmed as an input by clearing the corresponding bit in the DDR, or
programmed as an output by setting the corresponding bit in the DDR. The DDR for Port A, B, C,
and D are located at $04, $05, $06 and, $07 respectively. The DDRs are cleared by reset.
Note:
A “glitch” may occur on an I/O pin when selecting from an input to an output unless the
data register is rst preconditioned to the desired state before changing the
corresponding DDR bit from a “0” to a “1”.
3.2
Port A — Keyboard Interrupts (KBI)
Port A is congured for use as keyboard interrupts when the KBIE bit is set in the Miscellaneous
Control Register (MCR). Individual keyboard interrupt port pins are also maskable by setting
corresponding bits in the Keyboard Interrupt Mask Register.
See Section 5.2.2.4 for details on the keyboard interrupts.
3.3
PD6 — IRQ2
The port pin PD6 is congured as IRQ2 by setting the IRQ2E bit in the MCR. The external interrupt
IRQ2 behaves similar to IRQ except it is edge-triggered only, and does not have wake-up function
in STOP mode.
See Section 5.2.2.2 for details on the external interrupt IRQ2.
Figure 3-1 Port I/O Circuitry
INPUT
REGISTER
BIT
INPUT I/O
OUTPUT
I/O PIN
DATA DIRECTION
REGISTER BIT
LATCHED OUTPUT
DATA BIT
INTERNAL
MC68HC05
CONNECTIONS
TPG
24
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