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參數(shù)資料
| 型號： | MC68HC05SU3AP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 68/80頁 |
| 文件大?。?/td> | 328K |
| 代理商： | MC68HC05SU3AP |
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MOTOROLA
10-2
MC68HC05SU3A
ELECTRICAL SPECIFICATIONS
10
10.3
DC Electrical Characteristics
Table 10-1 DC Electrical Characteristics
(VDD=5.0Vdc ±10%, VSS=0Vdc, temperature range=0 to 70°C)
CHARACTERISTICS
SYMBOL
MINIMUM
TYPICAL
MAXIMUM
UNIT
Output voltage
ILOAD = –10A
ILOAD = +10A
VOH
VOL
VDD–0.1
—
0.1
V
Output high voltage (ILOAD=–0.8mA): All Ports
VOH
VDD–0.8
—
V
Output low voltage (ILOAD=+1.6mA): All Ports
VOL
—
0.4
V
Output high current
(VOH=2.5V) All ports
(VOH=2.0V) PB5-PB7 in low-current mode (25°C)
(VOH=2.0V) PB5-PB7 in low-current mode (0 to 70°C)
IOH
7
1.5
1.25
10
1.75
30
5
mA
Output low current
(VOL=2.5V) All ports, except PB0 and PB1
(VOL=3.0V) PB5-PB7 in low-current mode
(VOL=2.5V) PB0, PB1
(VOL=0.4V) PB0, PB1
IOL
7
2
40
10
3.5
70
20
30
4.8
—
mA
Total I/O port current
Either source or sink
IPORT
—
100
—
mA
Input high voltage
PA0-PA7, PB0, PB1, IRQ, RESET, OSC1
VIH
0.7
×V
DD
—VDD
V
Input low voltage
PA0-PA7, PB0, PB1, IRQ, RESET, OSC1
VIL
VSS
—
0.2
×V
DD
V
Supply current:
Run
Wait
Stop
25
°C
0
°C to +70°C (Standard)
IDD
—
5.0
1.3
8
10
7.5
2.0
20
30
mA
A
I/O ports high-Z leakage current
PA0-PA7, PB2-PB7, PC0-PC7, PD0-PD7
IIL
——
±10
A
Input current
IRQ, OSC1
IIN
——
±2
A
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, OSC2
COUT
CIN
—
12
8
pF
Low voltage reset threshold
VLVR
2.8
3.5
4.2
V
Pull-up resistor
PA0-PA7, PB2-PB7, PC0-PC7, PD0-PD7
PB0, PB1
RESET
IRQ
RPU
15
1.6
20
60
20
1.9
60
100
90
2.9
150
300
K
K
K
K
Notes:
(1) All values shown reect average measurements.
(2) Typical values at midpoint of voltage range, 25
°C only.
(3) Wait IDD: Only timer system active.
(4) Wait, Stop IDD: All ports congured as inputs, VIL=0.2Vdc, VIH=VDD–0.2Vdc.
(5) Run (operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 (fOSC=2.0MHz), all inputs 0.2Vdc from rail; no DC loads, less than 50pF on
all outputs, CL=20pF on OSC2.
(6) Stop IDD measured with OSC1=VSS.
(7) Wait IDD is affected linearly by the OSC2 capacitance.
TPG
68
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