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參數(shù)資料
| 型號： | MC68HC05T7B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 59/109頁 |
| 文件大?。?/td> | 9008K |
| 代理商： | MC68HC05T7B |
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Central Processor Unit (CPU)
CPU Registers
MC68HC705KJ1MC68HRC705KJ1MC68HLC705KJ1 — Rev. 3.0
Technical Data
MOTOROLA
Central Processor Unit (CPU)
49
4.6.5 Condition Code Register
The condition code register is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed.
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD or ADC operation. The
half-carry flag is required for binary-coded decimal (BCD) arithmetic
operations.
I — Interrupt Mask
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic 0, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is logic 1, the interrupt request is latched. Normally, the CPU
processes the latched interrupt request as soon as the interrupt mask
is cleared again.
A return from interrupt instruction (RTI) unstacks the CPU registers,
restoring the interrupt mask to its cleared state. After any reset, the
interrupt mask is set and can be cleared only by a software
instruction.
N — Negative Flag
The CPU sets the negative flag when an ALU operation produces a
negative result.
Bit 7
6
54
32
1
Bit 0
Read:
1
HI
N
Z
C
Write:
Reset:
1
1U
U
= Unimplemented
U = Unaffected
Figure 4-6. Condition Code Register (CCR)
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