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參數(shù)資料
| 型號(hào)： | MC68HC05X32 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁(yè)數(shù)： | 98/232頁(yè) |
| 文件大?。?/td> | 1095K |
| 代理商： | MC68HC05X32 |
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MOTOROLA
6-10
MC68HC05X16
Rev. 1
PROGRAMMABLE TIMER
6
The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
6.4.2
Output compare register 2 (OCR2)
The 16-bit output compare register 2 is made up of two 8-bit registers at locations $1E (MSB) and
$1F (LSB). The contents of the output compare register 2 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding output compare flag
(OCF2) in the timer status register is set and the output level (OLVL2) is transferred to pin TCMP2.
The output compare register 2 values and the output level bit should be changed after each
successful comparison to establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The
free-running counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register 2 containing the MSB ($1E), the output
compare function is inhibited until the LSB ($1F) is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB ($1F) will not inhibit the compare
2 function. The processor can write to either byte of the output compare register 2 without affecting
the other byte. The output level (OLVL2) bit is clocked to the output level register and hence to the
TCMP2 pin whether the output compare flag 2 (OCF2) is set or clear. The minimum time required
to update the output compare register 2 is a function of the program rather than the internal
hardware. Because the output compare flag 2 and the output compare register 2 are not defined
at power on, and not affected by reset, care must be taken when initializing output compare
functions with software. The following procedure is recommended:
–
–
–
Write to output compare high 2 to inhibit further compares;
Read the timer status register to clear OCF2 (if set);
Write to output compare low 2 to enable the output compare 2 function.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Output compare high 2
$001E
Undefined
Output compare low 2
$001F
Undefined
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PDF描述 |
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| MC68HC705X32 | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| MC68HC05X4 | HCMOS Microcontroller Unit |
| MC68HC05X4CDW | HCMOS Microcontroller Unit |
| MC68HC05X4DW | HCMOS Microcontroller Unit |
| MC68HC705X4 | HCMOS Microcontroller Unit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MC68HC05X4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05X4CDW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC05X4DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC08AB16A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC08AB16AD | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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