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參數(shù)資料
| 型號(hào)： | MC68HC08AS32AFUE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 288/296頁(yè) |
| 文件大?。?/td> | 3608K |
| 代理商： | MC68HC08AS32AFUE |
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MC68HC08AS32A — Rev. 1.1
Data Sheet
Freescale Semiconductor
91
TSIFR — Transmit Single Byte IFR with No CRC (Type 1 or 2) Bit
The TSIFR bit is used to request the BDLC to transmit the byte in the BDLC data
register (BDR, $003F) as a single byte IFR with no CRC. Typically, the byte
transmitted is a unique identifier or address of the transmitting (responding)
node. See Figure 4-20.
1 = If this bit is set prior to a valid EOD being received with no CRC error,
once the EOD symbol has been received the BDLC will attempt to
transmit the appropriate normalization bit followed by the byte in the
BDR.
0 = The TSIFR bit will be cleared automatically, once the BDLC
has successfully transmitted the byte in the BDR onto the
bus, or TEOD is set, or an error is detected on the bus.
If the programmer attempts to set the TSIFR bit immediately after the EOD symbol
has been received from the bus, the TSIFR bit will remain in the reset state and no
attempt will be made to transmit the IFR byte.
If a loss of arbitration occurs when the BDLC attempts to transmit and after the IFR
byte winning arbitration completes transmission, the BDLC will again attempt to
transmit the BDR (with no normalization bit). The BDLC will continue transmission
attempts until an error is detected on the bus, or TEOD is set, or the BDLC
transmission is successful.
If loss or arbitration occurs in the last two bits of the IFR byte, two additional 1 bits
will not be sent out because the BDLC will attempt to retransmit the byte in the
transmit shift register after the IRF byte winning arbitration completes transmission.
TMIFR1 — Transmit Multiple Byte IFR with CRC (Type 3) Bit
The TMIFR1 bit requests the BDLC to transmit the byte in the BDLC data
register (BDR) as the first byte of a multiple byte IFR with CRC or as a single
byte IFR with CRC. Response IFR bytes are still subject to J1850 message
length maximums (see 4.4.2 J1850 Frame Format and Figure 4-20).
If this bit is set prior to a valid EOD being received with no CRC error, once the
EOD symbol has been received the BDLC will attempt to transmit the
appropriate normalization bit followed by IFR bytes. The programmer should set
TEOD after the last IFR byte has been written into the BDR register. After TEOD
has been set and the last IFR byte has been transmitted, the CRC byte is
transmitted.
0 = The TMIFR1 bit will be cleared automatically – once the BDLC has
successfully transmitted the CRC byte and EOD symbol – by the
detection of an error on the multiplex bus or by a transmitter underrun
caused when the programmer does not write another byte to the BDR
after the TDRE interrupt.
If the TMIFR1 bit is set, the BDLC will attempt to transmit the normalization
symbol followed by the byte in the BDR. After the byte in the BDR has been
loaded into the transmit shift register, a TDRE interrupt (see 4.6.4 BDLC State
Vector Register) will occur similar to the main message transmit sequence.
The programmer should then load the next byte of the IFR into the BDR for
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| MC68HC08AS32AVFU | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64 |
| MC68HC08AS32VFNR2 | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQCC52 |
| MC68HC08AS32FNR2 | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQCC52 |
| MC68HC08AS32CFNR2 | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQCC52 |
| MC68HC08AZ0CFU | 8-BIT, EEPROM, 8.4 MHz, MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC08AZ0 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Advance Information |
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