Advance Information
MC68HC08AS20
—
Rev. 4.1
368
Freescale Semiconductor
21.5 5.0 Volt DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Output High Voltage
(I
Load
= –2.0 mA) All Ports, RESET
Output Low Voltage
(I
Load
= 1.6 mA) All Ports, RESET
Input High Voltage
All Ports, IRQ
s
, RESET, OSC1
Input Low Voltage
All Ports, IRQ
s
, RESET, OSC1
V
DD
+ V
DDA
/V
DDAREF
Supply Current
Run (see Note 3)
Wait (see Note 4)
Stop (see Note 5)
25
°
C
–40
°
C to +105
°
C
25
°
C with LVI Enabled
–40
°
C to +105
°
C with LVI Enabled
I/O Ports Hi-Z Leakage Current
Input Current
Capacitance
Ports (As Input or Output)
Low-Voltage Reset Inhibit
Low-Voltage Reset Recover
Low-Voltage Reset Inhibit/Recover Hysteresis
POR ReArm Voltage (see Note 6)
POR Reset Voltage (see Note 7)
POR Rise Time Ramp Rate (see Note 8)
High COP Disable Voltage (see Note 9)
V
OH
V
DD
–0.8
—
—
V
V
OL
—
—
0.4
V
V
IH
0.7 x V
DD
—
V
DD
V
V
IL
V
SS
—
0.3 x V
DD
V
I
DD
—
—
—
—
—
—
—
—
—
—
3.8
4.0
100
0
0
0.02
V
DD
—
—
—
—
—
—
—
—
—
—
4.0
4.2
200
—
—
—
30
15
5
50
400
500
±
1
±
1
12
8
4.2
4.4
500
200
800
—
mA
mA
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
I
L
I
IN
C
OUT
C
IN
V
LVII
V
LVIR
H
LVI
V
POR
V
PORRST
R
POR
V
HI
pF
V
V
mV
mV
mV
V/ms
V
V
DD
+ 2
NOTES:
1. V
DD
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
= –40
°
C to +105
°
C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25
°
C only.
3. Run (Operating) I
DD
measured using external square wave clock source (f
OP
= 8.4 MHz). All inputs 0.2 V from rail.
No dc loads. Less than 100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capaci-
tance linearly affects run I
DD
. Measured with all modules enabled.
4. Wait I
DD
measured
using external square wave clock source (f
OP
= 8.4 MHz). All inputs 0.2 Vdc from rail. No dc
loads. Less than 100 pF on all outputs, C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance
linearly affects wait I
DD
. Measured with all modules enabled.
5. Stop I
DD
measured with OSC1 = V
SS
.
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
8. If minimum V
DD
is not reached before the internal POR reset is released, RST must be driven low externally until
minimum V
DD
is reached.
9. See
13.9 COP Module During Break Interrupts
.