參數(shù)資料
型號(hào): MC68HC11A0CFN2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 39/158頁
文件大?。?/td> 3803K
代理商: MC68HC11A0CFN2
ELECTRICAL CHARACTERISTICS
MOTOROLA
TECHNICAL DATA
A-13
A
NOTES:
1. If this setup time is met, STRB acknowledges in the next cycle. If it is not met, the response may be delayed one
more cycle.
2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respec-
tively).
3. All timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted.
Table A-5a Peripheral Port Timing (MC68L11A8)
VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH
Characteristic
Symbol
1.0 MHz
2.0 MHz
Unit
Min
Max
Min
Max
Frequency of Operation (E-Clock Frequency)
fo
dc
1.0
dc
2.0
MHz
E-Clock Period
tcyc
1000
500
ns
Peripheral Data Setup Time
(MCU Read of Ports A, C, D, and E)
tPDSU
100
100
ns
Peripheral Data Hold Time
(MCU Read of Ports A, C, D, and E)
tPDH
50—50—
ns
Delay Time, Peripheral Data Write
MCU Write to Port A
MCU Writes to Ports B, C, and D
tPWD = 1/4 tcyc + 150 ns
tPWD
250
400
250
275
ns
Input Data Setup Time (Port C)
tIS
60—60—
ns
Input Data Hold Time (Port C)
tIH
100
100
ns
Delay Time, E Fall to STRB
tDEB = 1/4 tcyc + 150 ns
tDEB
400
275
ns
Setup Time, STRA Asserted to E Fall (Note 1)
tAES
0—0—ns
Delay Time, STRA Asserted to Port C Data Output Valid
tPCD
100
100
ns
Hold Time, STRA Negated to Port C Data
tPCH
10—10—
ns
Three-State Hold Time
tPCZ
150
150
ns
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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