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參數(shù)資料
| 型號： | MC68HC11A1CFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, 2 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 46/158頁 |
| 文件大小： | 776K |
| 代理商： | MC68HC11A1CFN2 |
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MOTOROLA
5-2
SERIAL COMMUNICATIONS INTERFACE
MC68HC11A8
TECHNICAL DATA
5
1. The idle line is brought to a logic one state prior to transmission/reception of a
character.
2. A start bit (logic zero) is used to indicate the start of a frame.
3. The data is transmitted and received least-significant-bit first.
4. A stop bit (logic one) is used to indicate the end of a frame. A frame consists of
a start bit, a character of eight or nine data bits, and a stop bit.
5. A break is defined as the transmission or reception of a low (logic zero) for at
least one complete frame time.
Figure 5-1 Data Format
5.3 Wake-Up Feature
The receiver wake-up feature reduces SCI service overhead in multiple receiver sys-
tems. Software in each receiver evaluates the first character(s) of each message. If
the message is intended for a different receiver, the SCI can be placed in a sleep mode
so that the rest of the message will not generate requests for service. Whenever a new
message is started, logic in the sleeping receivers causes them to wake up so they
can evaluate the initial character(s) of the new message.
A sleeping SCI receiver can be configured (using the WAKE control bit in serial com-
munications control register 1 (SCCR1)) to wake up using either of two methods: idle
line wake up or address mark wake up.
In idle line wake up, a sleeping receiver wakes up as soon as the RxD line becomes
idle. Idle is defined as a continuous logic high on the RxD line for ten (or eleven) full
bit times. Systems using this type of wake up must provide at least one character time
of idle between messages to wake up sleeping receivers but must not allow any idle
time between characters within a message.
In address mark wake up, the most significant bit (MSB) in a character is used to indi-
cate that the character is an address (1) or a data (0) character. Sleeping receivers will
wake up whenever an address character is received. Systems using this method for
wake up would set the MSB of the first character in each message and leave it clear
for all other characters in the message. Idle periods may be present within messages
and no idle time is required between messages for this wake up method.
5.4 Receive Data (RxD)
Receive data is the serial data which is applied through the input line and the serial
communications interface to the internal bus. The receiver circuitry clocks the input at
a rate equal to 16 times the baud rate and this time is referred to as the RT clock.
0
1
2
3
4
5
6
7
8
*
0
IDLE LINE
SCI DATA FORMAT
1
START
STOP
START
* CONTROL BIT M IN SCCR1 SELECTS EITHER 8-BIT OR 9-BIT DATA.
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| MC68HCP11A1CFN2 | HCMOS Single-Chip Microcontroller |
| MC68HCP11A1CFN3 | HCMOS Single-Chip Microcontroller |
| MC68HCP11A1CP2 | HCMOS Single-Chip Microcontroller |
| MC68HCP11A1CP3 | HCMOS Single-Chip Microcontroller |
| MC68HCP11A1MFN2 | HCMOS Single-Chip Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11A1CFN3 | 制造商:Rochester Electronics LLC 功能描述: |
| MC68HC11A1CFNE3 | 功能描述:8位微控制器 -MCU 8B MCU 256RAM A/D EE RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC68HC11A1CFNE3 | 制造商:Freescale Semiconductor 功能描述:8-BIT MICROCONTROLLER IC |
| MC68HC11A1CFNE3R | 功能描述:8位微控制器 -MCU 8B MCU 256RAM A/D EE RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC68HC11A1CFU2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
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