參數(shù)資料
型號： MC68HC11A1CFU2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64
封裝： QFP-64
文件頁數(shù)： 108/158頁
文件大?。?/td> 3803K
代理商： MC68HC11A1CFU2
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
TECHNICAL DATA
5-9
5
TCIE — Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI Interrupt if TC = 1
RIE — Receive Interrupt Enable
0 = RDRF and OR interrupts disabled
1 = SCI interrupt if RDRF or OR = 1
ILIE — Idle Line Interrupt Enable
0 = IDLE interrupts disabled
1 = SCI interrupt if IDLE = 1
TE — Transmit Enable
When the transmit enable bit is set, the transmit shift register output is applied to the
TxD line. Depending on the state of control bit M (SCCR1), a preamble of 10 (M = 0)
or 11 (M = 1) consecutive ones is transmitted when software sets the TE bit from a
cleared state. After loading the last byte in the serial communications data register and
receiving the TDRE flag, the user can clear TE. Transmission of the last byte will then
be completed before the transmitter gives up control of the TxD pin. While the trans-
mitter is active, the data direction register control for port D bit 1 is overridden and the
line is forced to be an output.
RE — Receive Enable
When the receive enable bit is set, the receiver is enabled. When RE is clear, the re-
ceiver is disabled and all of the status bits associated with the receiver (RDRF, IDLE,
OR, NF, and FE) are inhibited. While the receiver is enabled, the data direction register
control for port D bit 0 is overridden and the line is forced to be an input.
RWU — Receiver Wake Up
When the receiver wake-up bit is set by the user’s software, it puts the receiver to
sleep and enables the “wake up” function. If the WAKE bit is cleared, RWU is cleared
by the SCI logic after receiving 10 (M = 0) or 11 (M = 1) consecutive ones. If the WAKE
bit is set, RWU is cleared by the SCI logic after receiving a data word whose MSB is
set.
SBK — Send Break
If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11
(M = 1) zeros and then reverts to idle or sending data. If SBK remains set, the trans-
mitter will continually send whole blocks of zeros (sets of 10 or 11) until cleared. At the
completion of the break code, the transmitter sends at least one high bit to guarantee
recognition of a valid start bit. If the transmitter is currently empty and idle, setting and
clearing SBK is likely to queue two character times of break because the first break
transfers almost immediately to the shift register and the second is then queued into
the parallel transmit buffer.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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