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| 型號： | MC68HC11A1CFU2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 130/158頁 |
| 文件大?。?/td> | 3803K |
| 代理商： | MC68HC11A1CFU2 |
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PROGRAMMABLE TIMER, RTI, AND PULSE ACCUMULATOR
MOTOROLA
TECHNICAL DATA
8-3
8
Register OC1M is used to specify the bits of port A (I/O and timer port) which are to be
affected as a result of a successful OC1 compare. Register OC1D is used to specify
the data which is to be stored to the affected bits of port A as the result of a successful
OC1 compare. If an OC1 compare and another output compare occur during the same
E cycle and both attempt to alter the same port A line, the OC1 compare prevails.
This function allows control of multiple l/O pins automatically with a single output com-
pare.
Another intended use for the special l/O pin control on output compare 1 is to allow
more than one output compare to control a single l/O pin. This allows pulses as short
as one E clock cycle to be generated.
8.1.5 Timer Compare Force Register (CFORC)
The timer compare force register is used to force early output compare actions. The
CFORC register is an 8-bit write-only register. Reads of this location have no meaning
and always return logic zeros. Note that the compare force function is not generally
recommended for use with the output toggle function because a normal compare oc-
curring immediately before or after the force may result in undesirable operation.
FOC1-FOC5 — Force Output Compare x Action
0 = Has no meaning
1 = Causes action programmed for output compare x, except the OCxF flag bit is
not set.
Bits 2-0 — Not Implemented
These bits always read zero.
8.1.6 Output Compare 1 Mask Register (OC1M)
This register is used in conjunction with output compare 1 to specify the bits of port A
which are affected as a result of a successful OC1 compare.
The bits of the OC1M register correspond bit-for-bit with the lines of port A (lines 7
through 3 only). For each bit that is affected by the successful compare, the corre-
sponding bit in OC1M should be set to one.
7
654321
0
$100B
FOC1
FOC2
FOC3
FOC4
FOC5
0
CFORC
RESET
00000000
7
654321
0
$100C
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
0
OC1M
RESET
00000000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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