參數(shù)資料
型號: MC68HC11A1CP2
廠商: ABILIS SYSTEMS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝: PLASTIC, DIP-48
文件頁數(shù): 107/158頁
文件大小: 3803K
代理商: MC68HC11A1CP2
SERIAL COMMUNICATIONS INTERFACE
MC68HC11A8
5-8
TECHNICAL DATA
5
5.8.2 Serial Communications Control Register 1 (SCCR1)
The serial communications control register 1 (SCCR1) provides the control bits which:
(1) determine the word length, and (2) select the method used for the wake-up feature.
R8 — Receive Data Bit 8
If the M bit is set, this bit provides a storage location for the ninth bit in the receive data
character.
T8 —Transmit Data Bit 8
If the M bit is set, this bit provides a storage location for the ninth bit in the transmit
data character. It is not necessary to write to this bit for every character transmitted,
only when the sense is to be different than that for the previous character.
Bit 5 — Not Implemented
This bit always reads zero.
M — SCI Character Length
0 = 1 start bit, 8 data bits, 1 stop bit
1 = 1 start bit, 9 data bits, 1 stop bit
WAKE — Wake Up Method Select
0 = Idle Line
1 = Address Mark
Bits 2-0 — Not Implemented
These bits always read zero.
5.8.3 Serial Communications Control Register 2 (SCCR2)
The serial communications control register 2 (SCCR2) provides the control bits which
enable/disable individual SCI functions.
TIE — Transmit Interrupt Enable
0 = TDRE interrupts disabled
1 = SCI interrupt if TDRE = 1
7
6543210
$102C
R8
T8
0
M
WAKE
0
SCCR1
RESET
U
000000
7
6543210
$102D
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
SCCR2
RESET
00000000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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