參數(shù)資料
型號: MC68HC11A1MFN2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 95/158頁
文件大?。?/td> 3803K
代理商: MC68HC11A1MFN2
PARALLEL I/O
MOTOROLA
TECHNICAL DATA
4-3
4
4.4.1 Input Handshake Protocol
In the input handshake protocol, port C is a latching input port, STRA is an edge-sen-
sitive latch command from the external system that is driving port C, and STRB is a
“ready” output line controlled by logic in the MCU.
When a “ready” condition is recognized, the external device places data on the port C
lines, then pulses the STRA line. The active edge on the STRA line latches the port C
data into the PORTCL register, sets the STAF flag (optionally causing an interrupt),
and deasserts the STRB line. Deassertion of the STRB line automatically inhibits the
external device from strobing new data into port C. Reading the PORTCL latch register
(independent of clearing the STAF flag) asserts the STRB line, indicating that new
data may now be applied to port C.
The STRB line can be configured (with the PLS control bit) to be a pulse output (pulse
mode) or a static output (interlocked mode).
The port C data direction register bits should be cleared for each line that is to be used
as a latched input line. However, some port C lines can be used as latched inputs with
the input handshake protocol while, at the same time, using some port C lines as static
inputs, and some port C lines as static outputs. The input handshake protocol has no
effect on the use of port C lines as static inputs or as static outputs. Reads of the
PORTC data register always return the static logic level at the port C lines (for lines
configured as inputs). Writes to either the PORTC data register or the alternate latched
port C register (PORTCL) send information to the same port C output register without
affecting the input handshake strobes.
4.4.2 Output Handshake Protocol
In the output handshake protocol, port C is an output port, STRB is a “ready” output,
and STRA is an edge-sensitive acknowledge input signal, used to indicate to the MCU
that the output data has been accepted by the external device. In a variation of this
output handshake protocol, STRA is also used as an output-enable input, as well as
an edge-sensitive acknowledge input.
The MCU places data on the port C output lines and then indicates stable data is avail-
able by asserting the STRB line. The external device then processes the available
data and pulses the STRA line to indicate that new data may be placed on the port C
output lines. The active edge on the STRA line causes the STRB line to be deasserted
and the STAF status flag to be set. In response to the STAF bit being set, the program
transfers new data out of port C as required. Writing data to the PORTCL register
causes the data to appear on port C lines and asserts the STRB line.
There is a variation to the output handshake protocol that allows three-state operation
on port C. It is possible to directly connect this 8-bit parallel port to other three-state
devices with no additional parts.
While the STRA input line is inactive, all port C lines obey the data direction specified
by the data direction register so that lines which are configured as inputs are high im-
pedance. When the STRA line is activated, all port C lines are forced to outputs re-
gardless of the data in the data direction register. Note that in output handshake
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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